|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 6595 { 2275, 3, 1, 6, 570, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2275 = VAB
6598 { 2278, 3, 1, 6, 571, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2278 = VACCB
6601 { 2281, 3, 1, 6, 571, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2281 = VACCF
6602 { 2282, 3, 1, 6, 571, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2282 = VACCG
6603 { 2283, 3, 1, 6, 571, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2283 = VACCH
6604 { 2284, 3, 1, 6, 571, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2284 = VACCQ
6606 { 2286, 3, 1, 6, 570, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2286 = VAF
6607 { 2287, 3, 1, 6, 570, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2287 = VAG
6608 { 2288, 3, 1, 6, 570, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2288 = VAH
6610 { 2290, 3, 1, 6, 570, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2290 = VAQ
6612 { 2292, 3, 1, 6, 572, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2292 = VAVGB
6613 { 2293, 3, 1, 6, 572, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2293 = VAVGF
6614 { 2294, 3, 1, 6, 572, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2294 = VAVGG
6615 { 2295, 3, 1, 6, 572, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2295 = VAVGH
6617 { 2297, 3, 1, 6, 573, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2297 = VAVGLB
6618 { 2298, 3, 1, 6, 573, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2298 = VAVGLF
6619 { 2299, 3, 1, 6, 573, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2299 = VAVGLG
6620 { 2300, 3, 1, 6, 573, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2300 = VAVGLH
6621 { 2301, 3, 1, 6, 557, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2301 = VBPERM
6629 { 2309, 3, 1, 6, 628, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2309 = VCEQB
6630 { 2310, 3, 1, 6, 629, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2310 = VCEQBS
6631 { 2311, 3, 1, 6, 628, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2311 = VCEQF
6632 { 2312, 3, 1, 6, 629, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2312 = VCEQFS
6633 { 2313, 3, 1, 6, 628, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2313 = VCEQG
6634 { 2314, 3, 1, 6, 629, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2314 = VCEQGS
6635 { 2315, 3, 1, 6, 628, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2315 = VCEQH
6636 { 2316, 3, 1, 6, 629, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2316 = VCEQHS
6643 { 2323, 3, 1, 6, 630, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2323 = VCHB
6644 { 2324, 3, 1, 6, 631, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2324 = VCHBS
6645 { 2325, 3, 1, 6, 630, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2325 = VCHF
6646 { 2326, 3, 1, 6, 631, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2326 = VCHFS
6647 { 2327, 3, 1, 6, 630, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2327 = VCHG
6648 { 2328, 3, 1, 6, 631, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2328 = VCHGS
6649 { 2329, 3, 1, 6, 630, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2329 = VCHH
6650 { 2330, 3, 1, 6, 631, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2330 = VCHHS
6652 { 2332, 3, 1, 6, 632, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2332 = VCHLB
6653 { 2333, 3, 1, 6, 633, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2333 = VCHLBS
6654 { 2334, 3, 1, 6, 632, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2334 = VCHLF
6655 { 2335, 3, 1, 6, 633, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2335 = VCHLFS
6656 { 2336, 3, 1, 6, 632, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2336 = VCHLG
6657 { 2337, 3, 1, 6, 633, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2337 = VCHLGS
6658 { 2338, 3, 1, 6, 632, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2338 = VCHLH
6659 { 2339, 3, 1, 6, 633, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2339 = VCHLHS
6660 { 2340, 3, 1, 6, 576, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2340 = VCKSM
6705 { 2385, 3, 1, 6, 606, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2385 = VERLLVB
6706 { 2386, 3, 1, 6, 606, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2386 = VERLLVF
6707 { 2387, 3, 1, 6, 606, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2387 = VERLLVG
6708 { 2388, 3, 1, 6, 606, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2388 = VERLLVH
6715 { 2395, 3, 1, 6, 609, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2395 = VESLVB
6716 { 2396, 3, 1, 6, 609, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2396 = VESLVF
6717 { 2397, 3, 1, 6, 609, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2397 = VESLVG
6718 { 2398, 3, 1, 6, 609, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2398 = VESLVH
6725 { 2405, 3, 1, 6, 611, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2405 = VESRAVB
6726 { 2406, 3, 1, 6, 611, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2406 = VESRAVF
6727 { 2407, 3, 1, 6, 611, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2407 = VESRAVG
6728 { 2408, 3, 1, 6, 611, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2408 = VESRAVH
6735 { 2415, 3, 1, 6, 613, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2415 = VESRLVB
6736 { 2416, 3, 1, 6, 613, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2416 = VESRLVF
6737 { 2417, 3, 1, 6, 613, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2417 = VESRLVG
6738 { 2418, 3, 1, 6, 613, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2418 = VESRLVH
6740 { 2420, 3, 1, 6, 678, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2420 = VFADB
6754 { 2434, 3, 1, 6, 680, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2434 = VFASB
6756 { 2436, 3, 1, 6, 855, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2436 = VFCEDB
6757 { 2437, 3, 1, 6, 710, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2437 = VFCEDBS
6758 { 2438, 3, 1, 6, 705, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2438 = VFCESB
6759 { 2439, 3, 1, 6, 713, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2439 = VFCESBS
6761 { 2441, 3, 1, 6, 855, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2441 = VFCHDB
6762 { 2442, 3, 1, 6, 710, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2442 = VFCHDBS
6764 { 2444, 3, 1, 6, 855, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2444 = VFCHEDB
6765 { 2445, 3, 1, 6, 710, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2445 = VFCHEDBS
6766 { 2446, 3, 1, 6, 705, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2446 = VFCHESB
6767 { 2447, 3, 1, 6, 713, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2447 = VFCHESBS
6768 { 2448, 3, 1, 6, 705, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2448 = VFCHSB
6769 { 2449, 3, 1, 6, 713, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2449 = VFCHSBS
6771 { 2451, 3, 1, 6, 694, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2451 = VFDDB
6772 { 2452, 3, 1, 6, 695, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2452 = VFDSB
6775 { 2455, 3, 1, 6, 730, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2455 = VFEEBS
6777 { 2457, 3, 1, 6, 730, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2457 = VFEEFS
6779 { 2459, 3, 1, 6, 730, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2459 = VFEEHS
6780 { 2460, 3, 1, 6, 729, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2460 = VFEEZB
6781 { 2461, 3, 1, 6, 730, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2461 = VFEEZBS
6782 { 2462, 3, 1, 6, 729, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2462 = VFEEZF
6783 { 2463, 3, 1, 6, 730, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2463 = VFEEZFS
6784 { 2464, 3, 1, 6, 729, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2464 = VFEEZH
6785 { 2465, 3, 1, 6, 730, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2465 = VFEEZHS
6788 { 2468, 3, 1, 6, 732, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2468 = VFENEBS
6790 { 2470, 3, 1, 6, 732, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2470 = VFENEFS
6792 { 2472, 3, 1, 6, 732, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2472 = VFENEHS
6793 { 2473, 3, 1, 6, 731, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2473 = VFENEZB
6794 { 2474, 3, 1, 6, 732, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2474 = VFENEZBS
6795 { 2475, 3, 1, 6, 731, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2475 = VFENEZF
6796 { 2476, 3, 1, 6, 732, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2476 = VFENEZFS
6797 { 2477, 3, 1, 6, 731, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2477 = VFENEZH
6798 { 2478, 3, 1, 6, 732, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2478 = VFENEZHS
6802 { 2482, 3, 1, 6, 702, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2482 = VFKEDB
6803 { 2483, 3, 1, 6, 711, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2483 = VFKEDBS
6804 { 2484, 3, 1, 6, 705, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2484 = VFKESB
6805 { 2485, 3, 1, 6, 713, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2485 = VFKESBS
6806 { 2486, 3, 1, 6, 702, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2486 = VFKHDB
6807 { 2487, 3, 1, 6, 711, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2487 = VFKHDBS
6808 { 2488, 3, 1, 6, 702, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2488 = VFKHEDB
6809 { 2489, 3, 1, 6, 711, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2489 = VFKHEDBS
6810 { 2490, 3, 1, 6, 705, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2490 = VFKHESB
6811 { 2491, 3, 1, 6, 713, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2491 = VFKHESBS
6812 { 2492, 3, 1, 6, 705, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2492 = VFKHSB
6813 { 2493, 3, 1, 6, 713, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2493 = VFKHSBS
6831 { 2511, 3, 1, 6, 683, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2511 = VFMDB
6836 { 2516, 3, 1, 6, 685, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2516 = VFMSB
6849 { 2529, 3, 1, 6, 678, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2529 = VFSDB
6853 { 2533, 3, 1, 6, 680, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2533 = VFSSB
6866 { 2546, 3, 1, 6, 582, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2546 = VGFMB
6867 { 2547, 3, 1, 6, 582, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2547 = VGFMF
6868 { 2548, 3, 1, 6, 582, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2548 = VGFMG
6869 { 2549, 3, 1, 6, 582, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2549 = VGFMH
6986 { 2666, 3, 1, 6, 596, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2666 = VMEB
6987 { 2667, 3, 1, 6, 596, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2667 = VMEF
6988 { 2668, 3, 1, 6, 596, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2668 = VMEH
6990 { 2670, 3, 1, 6, 597, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2670 = VMHB
6991 { 2671, 3, 1, 6, 597, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2671 = VMHF
6992 { 2672, 3, 1, 6, 597, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2672 = VMHH
6994 { 2674, 3, 1, 6, 598, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2674 = VMLB
6996 { 2676, 3, 1, 6, 599, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2676 = VMLEB
6997 { 2677, 3, 1, 6, 599, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2677 = VMLEF
6998 { 2678, 3, 1, 6, 599, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2678 = VMLEH
6999 { 2679, 3, 1, 6, 598, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2679 = VMLF
7001 { 2681, 3, 1, 6, 600, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2681 = VMLHB
7002 { 2682, 3, 1, 6, 600, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2682 = VMLHF
7003 { 2683, 3, 1, 6, 600, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2683 = VMLHH
7004 { 2684, 3, 1, 6, 600, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2684 = VMLHW
7006 { 2686, 3, 1, 6, 601, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2686 = VMLOB
7007 { 2687, 3, 1, 6, 601, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2687 = VMLOF
7008 { 2688, 3, 1, 6, 601, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2688 = VMLOH
7010 { 2690, 3, 1, 6, 587, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2690 = VMNB
7011 { 2691, 3, 1, 6, 587, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2691 = VMNF
7012 { 2692, 3, 1, 6, 587, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2692 = VMNG
7013 { 2693, 3, 1, 6, 587, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2693 = VMNH
7015 { 2695, 3, 1, 6, 588, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2695 = VMNLB
7016 { 2696, 3, 1, 6, 588, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2696 = VMNLF
7017 { 2697, 3, 1, 6, 588, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2697 = VMNLG
7018 { 2698, 3, 1, 6, 588, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2698 = VMNLH
7020 { 2700, 3, 1, 6, 602, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2700 = VMOB
7021 { 2701, 3, 1, 6, 602, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2701 = VMOF
7022 { 2702, 3, 1, 6, 602, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2702 = VMOH
7025 { 2705, 3, 1, 6, 553, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2705 = VMRHB
7026 { 2706, 3, 1, 6, 553, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2706 = VMRHF
7027 { 2707, 3, 1, 6, 553, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2707 = VMRHG
7028 { 2708, 3, 1, 6, 553, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2708 = VMRHH
7030 { 2710, 3, 1, 6, 554, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2710 = VMRLB
7031 { 2711, 3, 1, 6, 554, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2711 = VMRLF
7032 { 2712, 3, 1, 6, 554, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2712 = VMRLG
7033 { 2713, 3, 1, 6, 554, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2713 = VMRLH
7038 { 2718, 3, 1, 6, 585, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2718 = VMXB
7039 { 2719, 3, 1, 6, 585, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2719 = VMXF
7040 { 2720, 3, 1, 6, 585, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2720 = VMXG
7041 { 2721, 3, 1, 6, 585, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2721 = VMXH
7043 { 2723, 3, 1, 6, 586, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2723 = VMXLB
7044 { 2724, 3, 1, 6, 586, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2724 = VMXLF
7045 { 2725, 3, 1, 6, 586, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2725 = VMXLG
7046 { 2726, 3, 1, 6, 586, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2726 = VMXLH
7047 { 2727, 3, 1, 6, 848, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2727 = VN
7048 { 2728, 3, 1, 6, 848, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2728 = VNC
7049 { 2729, 3, 1, 6, 574, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2729 = VNN
7050 { 2730, 3, 1, 6, 848, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2730 = VNO
7051 { 2731, 3, 1, 6, 574, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2731 = VNX
7052 { 2732, 3, 1, 6, 849, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2732 = VO
7053 { 2733, 3, 1, 6, 575, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2733 = VOC
7058 { 2738, 3, 1, 6, 560, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2738 = VPKF
7059 { 2739, 3, 1, 6, 560, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2739 = VPKG
7060 { 2740, 3, 1, 6, 560, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2740 = VPKH
7062 { 2742, 3, 1, 6, 563, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2742 = VPKLSF
7063 { 2743, 3, 1, 6, 564, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2743 = VPKLSFS
7064 { 2744, 3, 1, 6, 563, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2744 = VPKLSG
7065 { 2745, 3, 1, 6, 564, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2745 = VPKLSGS
7066 { 2746, 3, 1, 6, 563, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2746 = VPKLSH
7067 { 2747, 3, 1, 6, 564, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2747 = VPKLSHS
7069 { 2749, 3, 1, 6, 561, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2749 = VPKSF
7070 { 2750, 3, 1, 6, 562, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2750 = VPKSFS
7071 { 2751, 3, 1, 6, 561, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2751 = VPKSG
7072 { 2752, 3, 1, 6, 562, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2752 = VPKSGS
7073 { 2753, 3, 1, 6, 561, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2753 = VPKSH
7074 { 2754, 3, 1, 6, 562, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2754 = VPKSHS
7094 { 2774, 3, 1, 6, 620, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2774 = VSB
7100 { 2780, 3, 1, 6, 621, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2780 = VSCBIB
7101 { 2781, 3, 1, 6, 621, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2781 = VSCBIF
7102 { 2782, 3, 1, 6, 621, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2782 = VSCBIG
7103 { 2783, 3, 1, 6, 621, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2783 = VSCBIH
7104 { 2784, 3, 1, 6, 621, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2784 = VSCBIQ
7113 { 2793, 3, 1, 6, 622, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2793 = VSF
7114 { 2794, 3, 1, 6, 622, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2794 = VSG
7115 { 2795, 3, 1, 6, 622, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2795 = VSH
7116 { 2796, 3, 1, 6, 614, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2796 = VSL
7117 { 2797, 3, 1, 6, 615, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2797 = VSLB
7121 { 2801, 3, 1, 6, 622, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2801 = VSQ
7122 { 2802, 3, 1, 6, 616, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2802 = VSRA
7123 { 2803, 3, 1, 6, 617, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2803 = VSRAB
7125 { 2805, 3, 1, 6, 616, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2805 = VSRL
7126 { 2806, 3, 1, 6, 617, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2806 = VSRLB
7172 { 2852, 3, 1, 6, 623, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2852 = VSUMB
7174 { 2854, 3, 1, 6, 624, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2854 = VSUMGF
7175 { 2855, 3, 1, 6, 624, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2855 = VSUMGH
7176 { 2856, 3, 1, 6, 623, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2856 = VSUMH
7178 { 2858, 3, 1, 6, 625, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2858 = VSUMQF
7179 { 2859, 3, 1, 6, 625, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2859 = VSUMQG
7199 { 2879, 3, 1, 6, 579, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2879 = VX
7211 { 2891, 3, 1, 6, 682, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2891 = WFAXB
7218 { 2898, 3, 1, 6, 708, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2898 = WFCEXB
7219 { 2899, 3, 1, 6, 716, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2899 = WFCEXBS
7226 { 2906, 3, 1, 6, 708, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2906 = WFCHEXB
7227 { 2907, 3, 1, 6, 716, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2907 = WFCHEXBS
7230 { 2910, 3, 1, 6, 708, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2910 = WFCHXB
7231 { 2911, 3, 1, 6, 716, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2911 = WFCHXBS
7236 { 2916, 3, 1, 6, 696, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2916 = WFDXB
7246 { 2926, 3, 1, 6, 709, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2926 = WFKEXB
7247 { 2927, 3, 1, 6, 717, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2927 = WFKEXBS
7254 { 2934, 3, 1, 6, 709, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2934 = WFKHEXB
7255 { 2935, 3, 1, 6, 717, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2935 = WFKHEXBS
7258 { 2938, 3, 1, 6, 709, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2938 = WFKHXB
7259 { 2939, 3, 1, 6, 717, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, ImplicitList1, OperandInfo327, -1 ,nullptr }, // Inst #2939 = WFKHXBS
7289 { 2969, 3, 1, 6, 686, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2969 = WFMXB
7304 { 2984, 3, 1, 6, 682, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList3, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2984 = WFSXB