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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7136 case X86::DX: OpKind = MCK_DX; break;
gen/lib/Target/X86/X86GenCallingConv.inc 662 X86::CX, X86::DX
2231 X86::CX, X86::DX, X86::R8W, X86::R9W
2690 X86::AX, X86::DX, X86::CX
2959 X86::AX, X86::DX, X86::CX
3061 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3458 X86::AX, X86::DX, X86::CX, X86::R8W
3631 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
3831 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
gen/lib/Target/X86/X86GenInstrInfo.inc16596 static const MCPhysReg ImplicitList34[] = { X86::AX, X86::DX, 0 };
16597 static const MCPhysReg ImplicitList35[] = { X86::AX, X86::DX, X86::EFLAGS, 0 };
16603 static const MCPhysReg ImplicitList41[] = { X86::DX, 0 };
16604 static const MCPhysReg ImplicitList42[] = { X86::DX, X86::EDI, X86::DF, 0 };
16627 static const MCPhysReg ImplicitList65[] = { X86::DX, X86::AX, 0 };
16628 static const MCPhysReg ImplicitList66[] = { X86::DX, X86::EAX, 0 };
16629 static const MCPhysReg ImplicitList67[] = { X86::DX, X86::AL, 0 };
16630 static const MCPhysReg ImplicitList68[] = { X86::DX, X86::ESI, X86::DF, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1373 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
1383 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
1503 X86::AX, X86::CX, X86::DX, X86::BX,
lib/Target/X86/AsmParser/X86AsmParser.cpp 2314 if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
2723 Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
2732 Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
2746 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
2757 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 99 {codeview::RegisterId::DX, X86::DX},
620 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
632 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
669 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
670 return X86::DX;
705 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
741 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
lib/Target/X86/X86FastISel.cpp 1886 { &X86::GR16RegClass, X86::AX, X86::DX, {
1888 { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem
1890 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem
lib/Target/X86/X86ISelDAGToDAG.cpp 4828 LoReg = X86::AX; HiReg = X86::DX;
4829 ClrReg = X86::DX;
lib/Target/X86/X86InstructionSelector.cpp 1578 X86::DX,
1581 {X86::IDIV16r, X86::CWD, Copy, X86::DX, S}, // SRem
1583 {X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U}, // URem