reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenRegisterInfo.inc

 2797   { 8U, X86::EIP },
 2842   { 8U, X86::EIP },
 2964   { 8U, X86::EIP },
 3009   { 8U, X86::EIP },
 3052   { X86::EIP, -2U },
 3202   { X86::EIP, 8U },
 3352   { X86::EIP, 8U },
 3502   { X86::EIP, -2U },
 3652   { X86::EIP, 8U },
 3802   { X86::EIP, 8U },

lib/Target/X86/AsmParser/X86AsmParser.cpp

 1007       !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
 1027   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
 1028       IndexReg == X86::EIP || IndexReg == X86::RIP ||
 1080       (BaseReg == X86::RIP || BaseReg == X86::EIP)) {

lib/Target/X86/Disassembler/X86Disassembler.cpp

  608         baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP :

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

  217   if (BaseReg.getReg() == X86::EIP) {
  391       BaseReg == X86::EIP) {    // [disp32+rIP] in X86-64 mode

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

  316                     : X86::EIP; // Should have dwarf #8.
  361   unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;

lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp

  303     case X86::EIP: OS << "$eip"; break;

lib/Target/X86/X86RegisterInfo.cpp

   45     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
   48                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
  621   for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})