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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/X86/X86GenRegisterInfo.inc 4396 extern const TargetRegisterClass GR64RegClass;
References
gen/lib/Target/X86/X86GenFastISel.inc 400 return fastEmitInst_r(X86::VMOVSDto64Zrr, &X86::GR64RegClass, Op0, Op0IsKill);
403 return fastEmitInst_r(X86::MOVSDto64rr, &X86::GR64RegClass, Op0, Op0IsKill);
406 return fastEmitInst_r(X86::VMOVSDto64rr, &X86::GR64RegClass, Op0, Op0IsKill);
428 return fastEmitInst_r(X86::MMX_MOVD64from64rr, &X86::GR64RegClass, Op0, Op0IsKill);
483 return fastEmitInst_r(X86::JMP64r, &X86::GR64RegClass, Op0, Op0IsKill);
508 return fastEmitInst_r(X86::BSWAP64r, &X86::GR64RegClass, Op0, Op0IsKill);
543 return fastEmitInst_r(X86::LZCNT64rr, &X86::GR64RegClass, Op0, Op0IsKill);
641 return fastEmitInst_r(X86::POPCNT64rr, &X86::GR64RegClass, Op0, Op0IsKill);
799 return fastEmitInst_r(X86::TZCNT64rr, &X86::GR64RegClass, Op0, Op0IsKill);
830 return fastEmitInst_r(X86::BSF64rr, &X86::GR64RegClass, Op0, Op0IsKill);
1046 return fastEmitInst_r(X86::VCVTTSS2SI64Zrr, &X86::GR64RegClass, Op0, Op0IsKill);
1049 return fastEmitInst_r(X86::CVTTSS2SI64rr, &X86::GR64RegClass, Op0, Op0IsKill);
1052 return fastEmitInst_r(X86::VCVTTSS2SI64rr, &X86::GR64RegClass, Op0, Op0IsKill);
1080 return fastEmitInst_r(X86::VCVTTSD2SI64Zrr, &X86::GR64RegClass, Op0, Op0IsKill);
1083 return fastEmitInst_r(X86::CVTTSD2SI64rr, &X86::GR64RegClass, Op0, Op0IsKill);
1086 return fastEmitInst_r(X86::VCVTTSD2SI64rr, &X86::GR64RegClass, Op0, Op0IsKill);
1128 return fastEmitInst_r(X86::VCVTTSS2USI64Zrr, &X86::GR64RegClass, Op0, Op0IsKill);
1150 return fastEmitInst_r(X86::VCVTTSD2USI64Zrr, &X86::GR64RegClass, Op0, Op0IsKill);
1385 return fastEmitInst_r(X86::MOVSX64rr8, &X86::GR64RegClass, Op0, Op0IsKill);
1401 return fastEmitInst_r(X86::MOVSX64rr16, &X86::GR64RegClass, Op0, Op0IsKill);
1416 return fastEmitInst_r(X86::MOVSX64rr32, &X86::GR64RegClass, Op0, Op0IsKill);
2539 return fastEmitInst_r(X86::RETPOLINE_CALL64, &X86::GR64RegClass, Op0, Op0IsKill);
2542 return fastEmitInst_r(X86::CALL64r, &X86::GR64RegClass, Op0, Op0IsKill);
3044 return fastEmitInst_r(X86::VCVTSS2SI64Zrr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3047 return fastEmitInst_r(X86::CVTSS2SI64rr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3050 return fastEmitInst_r(X86::VCVTSS2SI64rr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3078 return fastEmitInst_r(X86::VCVTSD2SI64Zrr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3081 return fastEmitInst_r(X86::CVTSD2SI64rr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3084 return fastEmitInst_r(X86::VCVTSD2SI64rr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3116 return fastEmitInst_r(X86::VCVTSS2USI64Zrr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3138 return fastEmitInst_r(X86::VCVTSD2USI64Zrr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3612 return fastEmitInst_r(X86::VCVTTSS2SI64Zrr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3615 return fastEmitInst_r(X86::CVTTSS2SI64rr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3618 return fastEmitInst_r(X86::VCVTTSS2SI64rr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3646 return fastEmitInst_r(X86::VCVTTSD2SI64Zrr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3649 return fastEmitInst_r(X86::CVTTSD2SI64rr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3652 return fastEmitInst_r(X86::VCVTTSD2SI64rr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3684 return fastEmitInst_r(X86::VCVTTSS2SI64Zrrb_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3706 return fastEmitInst_r(X86::VCVTTSD2SI64Zrrb_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3738 return fastEmitInst_r(X86::VCVTTSS2USI64Zrr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3760 return fastEmitInst_r(X86::VCVTTSD2USI64Zrr_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3792 return fastEmitInst_r(X86::VCVTTSS2USI64Zrrb_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3814 return fastEmitInst_r(X86::VCVTTSD2USI64Zrrb_Int, &X86::GR64RegClass, Op0, Op0IsKill);
3874 return fastEmitInst_r(X86::EH_RETURN64, &X86::GR64RegClass, Op0, Op0IsKill);
4516 return fastEmitInst_r(X86::JMP64r_NT, &X86::GR64RegClass, Op0, Op0IsKill);
4554 return fastEmitInst_r(X86::CALL64r_NT, &X86::GR64RegClass, Op0, Op0IsKill);
4852 return fastEmitInst_r(X86::SEG_ALLOCA_64, &X86::GR64RegClass, Op0, Op0IsKill);
5886 return fastEmitInst_r(X86::WIN_ALLOCA_64, &X86::GR64RegClass, Op0, Op0IsKill);
6010 return fastEmitInst_rr(X86::ADD64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6202 return fastEmitInst_rr(X86::AND64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6971 return fastEmitInst_rr(X86::IMUL64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
7209 return fastEmitInst_rr(X86::OR64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
8161 return fastEmitInst_rr(X86::SUB64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
8835 return fastEmitInst_rr(X86::XOR64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
9387 return fastEmitInst_rr(X86::BEXTR64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
9417 return fastEmitInst_rr(X86::BT64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
9444 return fastEmitInst_rr(X86::BZHI64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
9480 return fastEmitInst_rr(X86::CMP64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
13697 return fastEmitInst_ri(X86::VPEXTRQZrr, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
13700 return fastEmitInst_ri(X86::PEXTRQrr, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
13703 return fastEmitInst_ri(X86::VPEXTRQrr, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
13782 return fastEmitInst_ri(X86::SHLDROT64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
13813 return fastEmitInst_ri(X86::RORX64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
13816 return fastEmitInst_ri(X86::SHRDROT64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
13852 return fastEmitInst_ri(X86::SHL64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
13888 return fastEmitInst_ri(X86::SAR64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
13924 return fastEmitInst_ri(X86::SHR64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14030 return fastEmitInst_ri(X86::BT64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14135 return fastEmitInst_ri(X86::ADD64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14150 return fastEmitInst_ri(X86::AND64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14165 return fastEmitInst_ri(X86::IMUL64rri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14180 return fastEmitInst_ri(X86::OR64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14195 return fastEmitInst_ri(X86::SUB64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14210 return fastEmitInst_ri(X86::XOR64ri32, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14226 return fastEmitInst_ri(X86::BEXTRI64ri, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14466 return fastEmitInst_ri(X86::ADD64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14481 return fastEmitInst_ri(X86::AND64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14496 return fastEmitInst_ri(X86::IMUL64rri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14511 return fastEmitInst_ri(X86::OR64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14526 return fastEmitInst_ri(X86::SUB64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
14541 return fastEmitInst_ri(X86::XOR64ri8, &X86::GR64RegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/X86/X86GenRegisterInfo.inc 5717 &X86::GR64RegClass,
5722 &X86::GR64RegClass,
5728 &X86::GR64RegClass,
5733 &X86::GR64RegClass,
5738 &X86::GR64RegClass,
5743 &X86::GR64RegClass,
5750 &X86::GR64RegClass,
5759 &X86::GR64RegClass,
5766 &X86::GR64RegClass,
5773 &X86::GR64RegClass,
5790 &X86::GR64RegClass,
5799 &X86::GR64RegClass,
5806 &X86::GR64RegClass,
5815 &X86::GR64RegClass,
5843 &X86::GR64RegClass,
5858 &X86::GR64RegClass,
5869 &X86::GR64RegClass,
5884 &X86::GR64RegClass,
5894 &X86::GR64RegClass,
5904 &X86::GR64RegClass,
5921 &X86::GR64RegClass,
5946 &X86::GR64RegClass,
5974 &X86::GR64RegClass,
5980 &X86::GR64RegClass,
5988 &X86::GR64RegClass,
5998 &X86::GR64RegClass,
6009 &X86::GR64RegClass,
6035 &X86::GR64RegClass,
6045 &X86::GR64RegClass,
6065 &X86::GR64RegClass,
6077 &X86::GR64RegClass,
6090 &X86::GR64RegClass,
6123 &X86::GR64RegClass,
6136 &X86::GR64RegClass,
6155 &X86::GR64RegClass,
6173 &X86::GR64RegClass,
6201 &X86::GR64RegClass,
7768 &X86::GR64RegClass,
lib/Target/X86/X86AsmPrinter.cpp 397 !X86::GR64RegClass.contains(Reg))
lib/Target/X86/X86CallFrameOptimization.cpp 542 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass);
543 Reg = MRI->createVirtualRegister(&X86::GR64RegClass);
lib/Target/X86/X86DomainReassignment.cpp 45 return X86::GR64RegClass.hasSubClassEq(RC) ||
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC))
lib/Target/X86/X86FastISel.cpp 781 RC = &X86::GR64RegClass;
1554 ResultReg = createResultReg(&X86::GR64RegClass);
1811 RC = &X86::GR64RegClass;
1900 { &X86::GR64RegClass, X86::RAX, X86::RDX, {
2685 case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;
3703 unsigned ResultReg = createResultReg(&X86::GR64RegClass);
3792 unsigned AddrReg = createResultReg(&X86::GR64RegClass);
lib/Target/X86/X86FrameLowering.cpp 586 const TargetRegisterClass *RegClass = &X86::GR64RegClass;
2017 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2033 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2081 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2114 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2194 if (X86::GR64RegClass.contains(Reg) ||
2211 if (!X86::GR64RegClass.contains(Reg) &&
lib/Target/X86/X86ISelLowering.cpp 182 addRegisterClass(MVT::i64, &X86::GR64RegClass);
2262 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2650 if (X86::GR64RegClass.contains(*I))
3241 RC = &X86::GR64RegClass;
3373 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
30817 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
30905 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
31041 Register BReg = MRI->createVirtualRegister(&X86::GR64RegClass);
31069 Register OReg64 = MRI->createVirtualRegister(&X86::GR64RegClass);
31070 Register TReg = MRI->createVirtualRegister(&X86::GR64RegClass);
45761 RC.hasSuperClassEq(&X86::GR64RegClass) ||
45833 return std::make_pair(0U, &X86::GR64RegClass);
45856 return std::make_pair(0U, &X86::GR64RegClass);
46050 : Size == 64 ? (is64Bit ? &X86::GR64RegClass : nullptr)
46187 if (X86::GR64RegClass.contains(*I))
46188 RC = &X86::GR64RegClass;
lib/Target/X86/X86InstrInfo.cpp 710 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2852 X86::GR64RegClass.hasSubClassEq(RC)) {
2898 if (X86::GR64RegClass.contains(DestReg)) {
2911 if (X86::GR64RegClass.contains(SrcReg)) {
2925 if (X86::GR64RegClass.contains(DestReg)) {
2934 } else if (X86::GR64RegClass.contains(SrcReg)) {
2972 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3112 if (X86::GR64RegClass.hasSubClassEq(RC))
4591 } else if (X86::GR64RegClass.contains(Reg)) {
7789 Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7790 Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7928 ? &X86::GR64RegClass
lib/Target/X86/X86InstructionSelector.cpp 177 return &X86::GR64RegClass;
217 if (X86::GR64RegClass.contains(Reg))
218 return &X86::GR64RegClass;
1452 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
lib/Target/X86/X86MachineFunctionInfo.cpp 25 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
lib/Target/X86/X86RegisterBankInfo.cpp 49 X86::GR64RegClass.hasSubClassEq(&RC) ||
lib/Target/X86/X86RegisterInfo.cpp 186 return &X86::GR64RegClass;
226 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
227 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
252 return &X86::GR64RegClass;
lib/Target/X86/X86SpeculativeLoadHardening.cpp 963 TargetAddrSSA.Initialize(MRI->createVirtualRegister(&X86::GR64RegClass));
1105 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass);
1156 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass);
2110 assert(OpRC->hasSuperClassEq(&X86::GR64RegClass) &&
2262 &X86::GR64RegClass};
2470 const TargetRegisterClass *AddrRC = &X86::GR64RegClass;
tools/llvm-exegesis/lib/X86/Target.cpp 672 if (X86::GR64RegClass.contains(Reg))