reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/X86/X86GenRegisterInfo.inc

 4331   extern const TargetRegisterClass GR8RegClass;

References

gen/lib/Target/X86/X86GenFastISel.inc

 5992   return fastEmitInst_rr(X86::ADD8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 6184   return fastEmitInst_rr(X86::AND8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 6953   return fastEmitInst_r(X86::MUL8r, &X86::GR8RegClass, Op1, Op1IsKill);
 7191   return fastEmitInst_rr(X86::OR8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7436   return fastEmitInst_r(X86::ROL8rCL, &X86::GR8RegClass, Op0, Op0IsKill);
 7538   return fastEmitInst_r(X86::ROR8rCL, &X86::GR8RegClass, Op0, Op0IsKill);
 7700   return fastEmitInst_r(X86::SHL8rCL, &X86::GR8RegClass, Op0, Op0IsKill);
 8026   return fastEmitInst_r(X86::SAR8rCL, &X86::GR8RegClass, Op0, Op0IsKill);
 8042   return fastEmitInst_r(X86::SHR8rCL, &X86::GR8RegClass, Op0, Op0IsKill);
 8143   return fastEmitInst_rr(X86::SUB8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 8817   return fastEmitInst_rr(X86::XOR8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 9462   return fastEmitInst_rr(X86::CMP8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
13623   return fastEmitInst_ri(X86::ADD8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
13652   return fastEmitInst_ri(X86::AND8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
13743   return fastEmitInst_ri(X86::OR8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
13834   return fastEmitInst_ri(X86::SHL8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
13870   return fastEmitInst_ri(X86::SAR8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
13906   return fastEmitInst_ri(X86::SHR8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
13942   return fastEmitInst_ri(X86::SUB8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
13971   return fastEmitInst_ri(X86::XOR8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
14570   return fastEmitInst_i(X86::MOV8ri, &X86::GR8RegClass, imm0);

gen/lib/Target/X86/X86GenRegisterInfo.inc

 5190   &X86::GR8RegClass,
 5195   &X86::GR8RegClass,
 5201   &X86::GR8RegClass,
 7703     &X86::GR8RegClass,

lib/Target/X86/X86AsmPrinter.cpp

  394   if (!X86::GR8RegClass.contains(Reg) &&

lib/Target/X86/X86DomainReassignment.cpp

   48          X86::GR8RegClass.hasSubClassEq(RC);
   69   if (X86::GR8RegClass.hasSubClassEq(SrcRC))
  224         (X86::GR8RegClass.contains(DstReg) ||
  229         (X86::GR8RegClass.contains(SrcReg) ||

lib/Target/X86/X86FastISel.cpp

  500     unsigned AndResult = createResultReg(&X86::GR8RegClass);
 1448     ResultReg = createResultReg(&X86::GR8RegClass);
 1484   ResultReg = createResultReg(&X86::GR8RegClass);
 1489     unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
 1490     unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
 1597     ResultReg = createResultReg(&X86::GR8RegClass);
 1784     RC = &X86::GR8RegClass;
 1879     { &X86::GR8RegClass,  X86::AX,  0, {
 2068       unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
 2069       unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
 2076         unsigned TmpReg = createResultReg(&X86::GR8RegClass);
 2976     unsigned ResultReg2 = createResultReg(&X86::GR8RegClass);

lib/Target/X86/X86FlagsCopyLowering.cpp

  346   PromoteRC = &X86::GR8RegClass;

lib/Target/X86/X86ISelLowering.cpp

  178   addRegisterClass(MVT::i8, &X86::GR8RegClass);
 3235           RC = &X86::GR8RegClass;
 3378       unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
 3469       unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
45758   return RC.hasSuperClassEq(&X86::GR8RegClass) ||
45831           return std::make_pair(0U, &X86::GR8RegClass);
45851         return std::make_pair(0U, &X86::GR8RegClass);
46047           Size == 8 ? (is64Bit ? &X86::GR8RegClass : &X86::GR8_NOREXRegClass)

lib/Target/X86/X86InstrInfo.cpp

 2978   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
 3073     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");

lib/Target/X86/X86InstructionSelector.cpp

  171       return &X86::GR8RegClass;
  208   } else if (RC == &X86::GR8RegClass) {
  223   if (X86::GR8RegClass.contains(Reg))
  224     return &X86::GR8RegClass;
  749   } else if (DstRC == &X86::GR8RegClass) {
 1037     Register FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
 1038     Register FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);

lib/Target/X86/X86RegisterBankInfo.cpp

   46   if (X86::GR8RegClass.hasSubClassEq(&RC) ||

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 2261       &X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass,

tools/llvm-exegesis/lib/X86/Target.cpp

  666   if (X86::GR8RegClass.contains(Reg))