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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7184 case X86::MM0: OpKind = MCK_VR64; break;
gen/lib/Target/X86/X86GenCallingConv.inc 452 X86::MM0, X86::MM1, X86::MM2
2824 if (unsigned Reg = State.AllocateReg(X86::MM0)) {
gen/lib/Target/X86/X86GenInstrInfo.inc16599 static const MCPhysReg ImplicitList37[] = { X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 0 };
16663 static const MCPhysReg ImplicitList101[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
16664 static const MCPhysReg ImplicitList102[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1236 { X86::MM0 },
2103 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2753 { 41U, X86::MM0 },
2814 { 29U, X86::MM0 },
2859 { 29U, X86::MM0 },
2920 { 41U, X86::MM0 },
2981 { 29U, X86::MM0 },
3026 { 29U, X86::MM0 },
3072 { X86::MM0, 41U },
3222 { X86::MM0, 29U },
3372 { X86::MM0, 29U },
3522 { X86::MM0, 41U },
3672 { X86::MM0, 29U },
3822 { X86::MM0, 29U },
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
lib/Target/X86/MCTargetDesc/X86InstComments.cpp 209 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 125 {codeview::RegisterId::MM0, X86::MM0},
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 182 EXPECT_THAT(setRegTo(X86::MM0, APInt(64, 0x1111222233334444ULL)),
186 IsMovValueFromStack(X86::MMX_MOVQ64rm, X86::MM0),