|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 4973 Inst.addOperand(MCOperand::createReg(X86::RAX));
7167 case X86::RAX: OpKind = MCK_RAX; break;
gen/lib/Target/X86/X86GenCallingConv.inc 843 if (unsigned Reg = State.AllocateReg(X86::RAX)) {
861 if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1437 if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1741 X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1833 if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1910 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1931 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2170 if (unsigned Reg = State.AllocateReg(X86::RAX)) {
2373 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2394 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2710 X86::RAX, X86::RDX, X86::RCX
3080 if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3098 if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3371 X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15
3401 X86::R15, X86::RBP, X86::RAX, X86::RDX
3478 X86::RAX, X86::RDX, X86::RCX, X86::R8
3573 if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3651 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3672 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3851 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3872 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
gen/lib/Target/X86/X86GenInstrInfo.inc16564 static const MCPhysReg ImplicitList2[] = { X86::RAX, X86::RCX, X86::RDX, 0 };
16565 static const MCPhysReg ImplicitList3[] = { X86::RAX, X86::RDX, X86::RBX, X86::EFLAGS, 0 };
16577 static const MCPhysReg ImplicitList15[] = { X86::RAX, X86::EFLAGS, 0 };
16578 static const MCPhysReg ImplicitList16[] = { X86::RAX, 0 };
16588 static const MCPhysReg ImplicitList26[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, 0 };
16589 static const MCPhysReg ImplicitList27[] = { X86::RAX, X86::RDX, X86::EFLAGS, 0 };
16595 static const MCPhysReg ImplicitList33[] = { X86::RAX, X86::RDX, 0 };
16601 static const MCPhysReg ImplicitList39[] = { X86::RAX, X86::RBX, X86::RCX, 0 };
16606 static const MCPhysReg ImplicitList44[] = { X86::RAX, X86::ECX, 0 };
16616 static const MCPhysReg ImplicitList54[] = { X86::RAX, X86::ESI, 0 };
16619 static const MCPhysReg ImplicitList57[] = { X86::RAX, X86::ECX, X86::EDX, 0 };
16620 static const MCPhysReg ImplicitList58[] = { X86::RAX, X86::RSI, 0 };
16621 static const MCPhysReg ImplicitList59[] = { X86::RAX, X86::RDX, X86::RSI, 0 };
16634 static const MCPhysReg ImplicitList72[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::EFLAGS, 0 };
16649 static const MCPhysReg ImplicitList87[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
16656 static const MCPhysReg ImplicitList94[] = { X86::RAX, X86::EDI, X86::DF, 0 };
16659 static const MCPhysReg ImplicitList97[] = { X86::RAX, X86::RSP, X86::EFLAGS, 0 };
16660 static const MCPhysReg ImplicitList98[] = { X86::RAX, X86::RDI, X86::DF, 0 };
16662 static const MCPhysReg ImplicitList100[] = { X86::RAX, X86::EFLAGS, X86::DF, 0 };
16664 static const MCPhysReg ImplicitList102[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
16671 static const MCPhysReg ImplicitList109[] = { X86::RAX, X86::RSI, X86::RDI, 0 };
16673 static const MCPhysReg ImplicitList111[] = { X86::RAX, X86::RDI, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1963 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
1993 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
2003 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2013 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2023 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
2033 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
2043 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
2053 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
2063 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
2073 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2083 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
2113 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
2123 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2133 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
2143 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
2163 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
2173 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
2183 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
2193 X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
2203 X86::RAX, X86::RCX, X86::RDX, X86::RBX,
2213 X86::RAX, X86::RCX, X86::RDX, X86::RSP,
2223 X86::RAX, X86::RCX, X86::RDX,
2233 X86::RAX, X86::RDX,
2712 { 0U, X86::RAX },
2879 { 0U, X86::RAX },
3055 { X86::RAX, 0U },
3205 { X86::RAX, -2U },
3355 { X86::RAX, -2U },
3505 { X86::RAX, 0U },
3655 { X86::RAX, -2U },
3805 { X86::RAX, -2U },
10016 static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
10018 static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
10020 static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10022 static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10024 static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
10040 static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10042 static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10044 static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, 0 };
gen/lib/Target/X86/X86GenSubtargetInfo.inc20831 && MI->getOperand(1).getReg() != X86::RAX
22437 && MI->getOperand(1).getReg() != X86::RAX
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
552 ALL_SIB_BASES
568 EA_BASES_64BIT
645 ALL_EA_BASES
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 156 {codeview::RegisterId::RAX, X86::RAX},
618 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
630 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
667 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
703 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
739 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
740 return X86::RAX;
lib/Target/X86/X86FastISel.cpp 1269 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
1900 { &X86::GR64RegClass, X86::RAX, X86::RDX, {
1901 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
1903 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
2947 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
lib/Target/X86/X86FrameLowering.cpp 200 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
264 unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
325 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
587 const Register SizeReg = InProlog ? X86::RAX
644 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
797 unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
1252 .addReg(X86::RAX, RegState::Kill)
1271 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1275 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1294 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
2149 BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2461 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
lib/Target/X86/X86ISelDAGToDAG.cpp 4392 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX;
4649 LoReg = X86::RAX;
4733 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
4837 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
lib/Target/X86/X86ISelLowering.cpp 2632 X86::RAX : X86::EAX;
17984 X86::RAX, X86II::MO_TLSGD);
18000 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
18153 unsigned Reg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
23820 LO = DAG.getCopyFromReg(Chain, DL, X86::RAX, MVT::i64, SDValue(N1, 1));
24294 return Subtarget.isTarget64BitLP64() ? X86::RAX : X86::EAX;
26702 Reg = X86::RAX; size = 8;
28290 Regs64bit ? X86::RAX : X86::EAX,
28344 Regs64bit ? X86::RAX : X86::EAX,
30098 .addReg(X86::RAX, RegState::ImplicitDefine);
30122 .addReg(IsLP64 ? X86::RAX : X86::EAX);
30255 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
45800 return std::make_pair(X86::RAX, &X86::GR64_ADRegClass);
46056 case X86::RAX:
lib/Target/X86/X86InstrInfo.cpp 7908 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7936 .addReg(is64Bit ? X86::RAX : X86::EAX);
lib/Target/X86/X86InstructionSelector.cpp 1595 X86::RAX,
1598 {X86::IDIV64r, X86::CQO, Copy, X86::RAX, S}, // SDiv
1600 {X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U}, // UDiv
lib/Target/X86/X86MCInstLower.cpp 303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
330 if (Op0 == X86::RAX && Op1 == X86::EAX)
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
739 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
997 BaseReg = X86::RAX;
1024 IndexReg = X86::RAX;
1030 IndexReg = X86::RAX;
1041 IndexReg = X86::RAX;
1047 IndexReg = X86::RAX;
1053 IndexReg = X86::RAX;
2073 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
lib/Target/X86/X86SelectionDAGInfo.cpp 56 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
127 ValReg = X86::RAX;
lib/Target/X86/X86WinAllocaExpander.cpp 219 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX;
233 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX;
247 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX;
unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp 54 Check({}, MCInstBuilder(MOV64ri32).addReg(RAX).addImm(42), 0x48, 0xc7, 0xc0,
unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp 35 X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
unittests/tools/llvm-exegesis/X86/SnippetFileTest.cpp 83 ElementsAre(RegisterInitialValueIs(X86::RAX, 15),
unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp 408 Mov.getValueFor(Mov.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
414 Add.getValueFor(Add.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);