|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7183 case X86::RIP: OpKind = MCK_Reg77; break;
gen/lib/Target/X86/X86GenRegisterInfo.inc 1593 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP,
1603 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP,
1823 X86::RIP, X86::RBP,
1933 X86::RIP,
1963 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
2013 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2023 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
2033 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
2073 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2123 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2193 X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
2243 X86::RBP, X86::RIP,
2313 X86::RIP,
2728 { 16U, X86::RIP },
2895 { 16U, X86::RIP },
3061 { X86::RIP, 16U },
3211 { X86::RIP, -2U },
3361 { X86::RIP, -2U },
3511 { X86::RIP, 16U },
3661 { X86::RIP, -2U },
3811 { X86::RIP, -2U },
lib/Target/X86/AsmParser/X86AsmParser.cpp 1007 !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
1027 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
1028 IndexReg == X86::EIP || IndexReg == X86::RIP ||
1080 (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1126 if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1875 if (RegNo == X86::RIP)
2004 if (Reg == X86::RIP)
2277 if (BaseReg == X86::RIP)
2280 if (IndexReg == X86::RIP)
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
609 X86::RIP);
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 390 if (BaseReg == X86::RIP ||
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 315 ? X86::RIP // Should have dwarf #16.
361 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
543 if (BaseReg.getReg() == X86::RIP)
lib/Target/X86/X86AsmPrinter.cpp 285 BaseReg.getReg() == X86::RIP)
lib/Target/X86/X86ExpandPseudo.cpp 93 .addReg(X86::RIP)
lib/Target/X86/X86FastISel.cpp 755 AM.Base.Reg = X86::RIP;
784 StubAM.Base.Reg = X86::RIP;
1075 AM.Base.Reg = X86::RIP;
3510 MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0);
3785 PICBase = X86::RIP;
lib/Target/X86/X86FrameLowering.cpp 187 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
2150 .addReg(X86::RIP)
2502 .addReg(X86::RIP)
lib/Target/X86/X86ISelDAGToDAG.cpp 98 return RegNode->getReg() == X86::RIP;
1467 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
1502 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
lib/Target/X86/X86ISelLowering.cpp30247 .addReg(X86::RIP)
30544 .addReg(X86::RIP)
30911 .addReg(X86::RIP)
31046 .addReg(X86::RIP)
lib/Target/X86/X86InstrInfo.cpp 606 if (BaseReg == 0 || BaseReg == X86::RIP)
3996 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5306 PICBase = X86::RIP;
7777 .addReg(X86::RIP)
7792 .addReg(X86::RIP)
8086 if (MI.readsRegister(X86::RIP, &RI) ||
8087 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
8088 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
lib/Target/X86/X86InstructionSelector.cpp 616 AM.Base.Reg = X86::RIP;
1476 PICBase = X86::RIP;
lib/Target/X86/X86MCInstLower.cpp 921 .addReg(X86::RIP)
937 .addReg(X86::RIP)
lib/Target/X86/X86RegisterInfo.cpp 45 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
48 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
535 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
621 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1119 .addReg(/*Base*/ X86::RIP)
1159 .addReg(/*Base*/ X86::RIP)
1720 if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP &&
1972 } else if (BaseMO.getReg() == X86::RIP ||
1984 << (BaseMO.getReg() == X86::RIP ? "RIP-relative" : "no-base")
2503 .addReg(/*Base*/ X86::RIP)
2545 .addReg(/*Base*/ X86::RIP)