|
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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenAsmMatcher.inc 5042 Inst.addOperand(MCOperand::createReg(X86::ST0));
7304 case X86::ST0: OpKind = MCK_ST0; break;
gen/lib/Target/X86/X86GenInstrInfo.inc16592 static const MCPhysReg ImplicitList30[] = { X86::ST0, X86::FPCW, 0 };
16599 static const MCPhysReg ImplicitList37[] = { X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 0 };
16663 static const MCPhysReg ImplicitList101[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
16664 static const MCPhysReg ImplicitList102[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1268 { X86::ST0 },
2393 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2745 { 33U, X86::ST0 },
2798 { 12U, X86::ST0 },
2843 { 11U, X86::ST0 },
2912 { 33U, X86::ST0 },
2965 { 12U, X86::ST0 },
3010 { 11U, X86::ST0 },
3088 { X86::ST0, 33U },
3238 { X86::ST0, 12U },
3388 { X86::ST0, 11U },
3538 { X86::ST0, 33U },
3688 { X86::ST0, 12U },
3838 { X86::ST0, 11U },
lib/Target/X86/AsmParser/X86AsmParser.cpp 1139 if (RegNo == X86::ST0) {
1152 case 0: RegNo = X86::ST0; break;
lib/Target/X86/Disassembler/X86Disassembler.cpp 718 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp 483 if (Reg == X86::ST0)
lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp 441 if (Reg == X86::ST0)
lib/Target/X86/X86FloatingPoint.cpp 204 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
847 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
1105 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
1151 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
1643 Op.setReg(X86::ST0 + FPReg);
lib/Target/X86/X86RegisterInfo.cpp 571 Reserved.set(X86::ST0 + n);
tools/llvm-exegesis/lib/X86/Target.cpp 476 if (Reg != X86::ST0)
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 293 EXPECT_THAT(setRegTo(X86::ST0, APInt(32, 0x11112222ULL)),
313 EXPECT_THAT(setRegTo(X86::ST0, APInt(64, 0x1111222233334444ULL)),
322 EXPECT_THAT(setRegTo(X86::ST0, APInt(80, "11112222333344445555", 16)),