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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenRegisterInfo.inc 4515 { 8, 8, 8, VTLists+0 }, // GR8
4516 { 8, 8, 8, VTLists+0 }, // GRH8
4517 { 8, 8, 8, VTLists+0 }, // GR8_NOREX
4518 { 8, 8, 8, VTLists+0 }, // GR8_ABCD_H
4519 { 8, 8, 8, VTLists+0 }, // GR8_ABCD_L
4520 { 16, 16, 16, VTLists+2 }, // GRH16
4521 { 16, 16, 16, VTLists+2 }, // GR16
4522 { 16, 16, 16, VTLists+2 }, // GR16_NOREX
4523 { 16, 16, 16, VTLists+24 }, // VK1
4524 { 16, 16, 16, VTLists+32 }, // VK16
4525 { 16, 16, 16, VTLists+26 }, // VK2
4526 { 16, 16, 16, VTLists+28 }, // VK4
4527 { 16, 16, 16, VTLists+30 }, // VK8
4528 { 16, 16, 16, VTLists+32 }, // VK16WM
4529 { 16, 16, 16, VTLists+24 }, // VK1WM
4530 { 16, 16, 16, VTLists+26 }, // VK2WM
4531 { 16, 16, 16, VTLists+28 }, // VK4WM
4532 { 16, 16, 16, VTLists+30 }, // VK8WM
4533 { 16, 16, 16, VTLists+2 }, // SEGMENT_REG
4534 { 16, 16, 16, VTLists+2 }, // GR16_ABCD
4535 { 16, 16, 16, VTLists+2 }, // FPCCR
4536 { 32, 32, 16, VTLists+56 }, // VK16PAIR
4537 { 32, 32, 16, VTLists+56 }, // VK1PAIR
4538 { 32, 32, 16, VTLists+56 }, // VK2PAIR
4539 { 32, 32, 16, VTLists+56 }, // VK4PAIR
4540 { 32, 32, 16, VTLists+56 }, // VK8PAIR
4541 { 32, 32, 16, VTLists+56 }, // VK16PAIR_with_sub_mask_0_in_VK16WM
4542 { 32, 32, 32, VTLists+10 }, // FR32X
4543 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP
4544 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS
4545 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
4546 { 32, 32, 32, VTLists+4 }, // DEBUG_REG
4547 { 32, 32, 32, VTLists+10 }, // FR32
4548 { 32, 32, 32, VTLists+4 }, // GR32
4549 { 32, 32, 32, VTLists+4 }, // GR32_NOSP
4550 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
4551 { 32, 32, 32, VTLists+4 }, // GR32_NOREX
4552 { 32, 32, 32, VTLists+34 }, // VK32
4553 { 32, 32, 32, VTLists+4 }, // GR32_NOREX_NOSP
4554 { 32, 32, 32, VTLists+10 }, // RFP32
4555 { 32, 32, 32, VTLists+34 }, // VK32WM
4556 { 32, 32, 32, VTLists+4 }, // GR32_ABCD
4557 { 32, 32, 32, VTLists+4 }, // GR32_TC
4558 { 32, 32, 32, VTLists+4 }, // GR32_ABCD_and_GR32_TC
4559 { 32, 32, 32, VTLists+4 }, // GR32_AD
4560 { 32, 32, 32, VTLists+4 }, // GR32_BPSP
4561 { 32, 32, 32, VTLists+4 }, // GR32_BSI
4562 { 32, 32, 32, VTLists+4 }, // GR32_CB
4563 { 32, 32, 32, VTLists+4 }, // GR32_DC
4564 { 32, 32, 32, VTLists+4 }, // GR32_DIBP
4565 { 32, 32, 32, VTLists+4 }, // GR32_SIDI
4566 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
4567 { 32, 32, 32, VTLists+4 }, // CCR
4568 { 32, 32, 32, VTLists+4 }, // DFCCR
4569 { 32, 32, 32, VTLists+4 }, // GR32_ABCD_and_GR32_BSI
4570 { 32, 32, 32, VTLists+4 }, // GR32_AD_and_GR32_DC
4571 { 32, 32, 32, VTLists+4 }, // GR32_BPSP_and_GR32_DIBP
4572 { 32, 32, 32, VTLists+4 }, // GR32_BPSP_and_GR32_TC
4573 { 32, 32, 32, VTLists+4 }, // GR32_BSI_and_GR32_SIDI
4574 { 32, 32, 32, VTLists+4 }, // GR32_CB_and_GR32_DC
4575 { 32, 32, 32, VTLists+4 }, // GR32_DIBP_and_GR32_SIDI
4576 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
4577 { 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
4578 { 64, 64, 32, VTLists+12 }, // RFP64
4579 { 64, 64, 64, VTLists+12 }, // FR64X
4580 { 64, 64, 64, VTLists+6 }, // GR64
4581 { 64, 64, 64, VTLists+6 }, // CONTROL_REG
4582 { 64, 64, 64, VTLists+12 }, // FR64
4583 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_8bit
4584 { 64, 64, 64, VTLists+6 }, // GR64_NOSP
4585 { 64, 64, 64, VTLists+6 }, // GR64_TC
4586 { 64, 64, 64, VTLists+6 }, // GR64_NOREX
4587 { 64, 64, 64, VTLists+6 }, // GR64_TCW64
4588 { 64, 64, 64, VTLists+6 }, // GR64_TC_with_sub_8bit
4589 { 64, 64, 64, VTLists+6 }, // GR64_NOSP_and_GR64_TC
4590 { 64, 64, 64, VTLists+6 }, // GR64_TCW64_with_sub_8bit
4591 { 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_TCW64
4592 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_16bit_in_GR16_NOREX
4593 { 64, 64, 64, VTLists+36 }, // VK64
4594 { 64, 64, 64, VTLists+54 }, // VR64
4595 { 64, 64, 64, VTLists+6 }, // GR64_NOREX_NOSP
4596 { 64, 64, 64, VTLists+6 }, // GR64_NOREX_and_GR64_TC
4597 { 64, 64, 64, VTLists+6 }, // GR64_NOSP_and_GR64_TCW64
4598 { 64, 64, 64, VTLists+6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
4599 { 64, 64, 64, VTLists+36 }, // VK64WM
4600 { 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
4601 { 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
4602 { 64, 64, 64, VTLists+6 }, // GR64_NOREX_NOSP_and_GR64_TC
4603 { 64, 64, 64, VTLists+6 }, // GR64_NOREX_and_GR64_TCW64
4604 { 64, 64, 64, VTLists+6 }, // GR64_ABCD
4605 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_TC
4606 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
4607 { 64, 64, 64, VTLists+6 }, // GR64_AD
4608 { 64, 64, 64, VTLists+6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
4609 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP
4610 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BSI
4611 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_CB
4612 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DC
4613 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DIBP
4614 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_SIDI
4615 { 64, 64, 64, VTLists+6 }, // GR64_and_LOW32_ADDR_ACCESS
4616 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
4617 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
4618 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
4619 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
4620 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
4621 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
4622 { 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
4623 { 80, 80, 32, VTLists+8 }, // RST
4624 { 80, 80, 32, VTLists+14 }, // RFP80
4625 { 80, 80, 32, VTLists+14 }, // RFP80_7
4626 { 128, 128, 128, VTLists+16 }, // VR128X
4627 { 128, 128, 128, VTLists+16 }, // VR128
4628 { 128, 128, 128, VTLists+38 }, // BNDR
4629 { 256, 256, 256, VTLists+40 }, // VR256X
4630 { 256, 256, 256, VTLists+40 }, // VR256
4631 { 512, 512, 512, VTLists+47 }, // VR512
4632 { 512, 512, 512, VTLists+47 }, // VR512_0_15