reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
650 tmp = fieldFromInstruction(insn, 0, 4); 654 if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 657 if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 660 if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 663 if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 666 if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 669 if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 672 if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 675 if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 678 tmp = fieldFromInstruction(insn, 6, 4); 680 tmp = fieldFromInstruction(insn, 0, 6); 684 tmp = fieldFromInstruction(insn, 0, 6); 688 tmp = fieldFromInstruction(insn, 6, 4); 690 tmp = fieldFromInstruction(insn, 0, 6); 694 tmp = fieldFromInstruction(insn, 0, 6); 698 tmp = fieldFromInstruction(insn, 6, 4); 700 tmp = fieldFromInstruction(insn, 0, 6); 704 if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 707 if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 710 if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 713 tmp = fieldFromInstruction(insn, 0, 10); 717 tmp = fieldFromInstruction(insn, 0, 10); 721 if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 724 if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 727 if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 730 if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 733 if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 736 if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 739 if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 742 tmp = fieldFromInstruction(insn, 22, 4); 745 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 746 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 751 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 752 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 756 tmp = fieldFromInstruction(insn, 22, 4); 759 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 760 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 765 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 766 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 770 tmp = fieldFromInstruction(insn, 22, 4); 773 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 774 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 778 if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 781 if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 784 if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 788 tmp |= fieldFromInstruction(insn, 0, 10) << 10; 789 tmp |= fieldFromInstruction(insn, 16, 10) << 0; 794 tmp |= fieldFromInstruction(insn, 0, 10) << 10; 795 tmp |= fieldFromInstruction(insn, 16, 10) << 0;