reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
650 tmp = fieldFromInstruction(insn, 0, 4); 651 if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 678 tmp = fieldFromInstruction(insn, 6, 4); 679 if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 680 tmp = fieldFromInstruction(insn, 0, 6); 681 MI.addOperand(MCOperand::createImm(tmp)); 684 tmp = fieldFromInstruction(insn, 0, 6); 685 MI.addOperand(MCOperand::createImm(tmp)); 688 tmp = fieldFromInstruction(insn, 6, 4); 689 if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 690 tmp = fieldFromInstruction(insn, 0, 6); 691 MI.addOperand(MCOperand::createImm(tmp)); 694 tmp = fieldFromInstruction(insn, 0, 6); 695 if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 698 tmp = fieldFromInstruction(insn, 6, 4); 699 if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 700 tmp = fieldFromInstruction(insn, 0, 6); 701 if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 713 tmp = fieldFromInstruction(insn, 0, 10); 714 MI.addOperand(MCOperand::createImm(tmp)); 717 tmp = fieldFromInstruction(insn, 0, 10); 718 if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 742 tmp = fieldFromInstruction(insn, 22, 4); 743 if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 744 tmp = 0x0; 745 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 746 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 747 MI.addOperand(MCOperand::createImm(tmp)); 750 tmp = 0x0; 751 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 752 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 753 MI.addOperand(MCOperand::createImm(tmp)); 756 tmp = fieldFromInstruction(insn, 22, 4); 757 if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 758 tmp = 0x0; 759 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 760 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 761 MI.addOperand(MCOperand::createImm(tmp)); 764 tmp = 0x0; 765 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 766 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 767 if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 770 tmp = fieldFromInstruction(insn, 22, 4); 771 if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 772 tmp = 0x0; 773 tmp |= fieldFromInstruction(insn, 0, 10) << 6; 774 tmp |= fieldFromInstruction(insn, 16, 6) << 0; 775 if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 787 tmp = 0x0; 788 tmp |= fieldFromInstruction(insn, 0, 10) << 10; 789 tmp |= fieldFromInstruction(insn, 16, 10) << 0; 790 MI.addOperand(MCOperand::createImm(tmp)); 793 tmp = 0x0; 794 tmp |= fieldFromInstruction(insn, 0, 10) << 10; 795 tmp |= fieldFromInstruction(insn, 16, 10) << 0; 796 if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }