reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

  112       Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc),

lib/CodeGen/GlobalISel/IRTranslator.cpp

 1835   auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst);

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

 3823   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
 3826   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
 3837   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
 3995   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
 3999     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
 4005     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
 4011     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
 4185     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
 4257     auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 1364   auto And = B.buildAnd(S1, Lt0, NeTrunc);
 1412   auto SignBit = B.buildAnd(S32, Hi, SignBitMask);
 1423   auto Tmp0 = B.buildAnd(S64, Src, Not);
 1812     B.buildAnd(DstReg, AndMaskSrc, B.buildConstant(S32, Mask >> Shift));

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

 1640       ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0);

unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

  584   auto And = B.buildAnd(V5S32, Op0, Op1);
  638   auto And = B.buildAnd(v2s32, Val0, Val1);
  718   B.buildAnd(PhiTy, Phi.getReg(0), Phi.getReg(0));

unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

  114   auto MIBAnd = B.buildAnd(s64, Copies[0], Copies[1]);