|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63136 /*137815*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::ADDC),// ->137831
gen/lib/Target/AVR/AVRGenDAGISel.inc 1000 /* 1705*/ /*SwitchOpcode*/ 68, TARGET_VAL(ISD::ADDC),// ->1776
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 704 /* 1226*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::ADDC),// ->1290
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 1969 /* 4077*/ /*SwitchOpcode*/ 24|128,2/*280*/, TARGET_VAL(ISD::ADDC),// ->4361
4213 /* 8463*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::ADDC),// ->8630
gen/lib/Target/Mips/MipsGenDAGISel.inc21377 /* 39879*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::ADDC),// ->39964
gen/lib/Target/Mips/MipsGenFastISel.inc 3407 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc57868 /*123058*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::ADDC),// ->123094
gen/lib/Target/PowerPC/PPCGenDAGISel.inc24988 /* 60246*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::ADDC),// ->60318
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3231 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3459 case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
3516 case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2214 /* 4075*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::ADDC),// ->4113
include/llvm/CodeGen/TargetLowering.h 2278 case ISD::ADDC:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1499 case ISD::ADDC: return visitADDC(N);
2512 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2672 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1766 case ISD::ADDC:
2161 ISD::ADDC : ISD::SUBC,
2167 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2263 if (N->getOpcode() == ISD::ADDC) {
2264 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3065 case ISD::ADDC:
3674 case ISD::ADDC:
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 285 case ISD::ADDC: return "addc";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 5728 bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) &&
5731 Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
lib/CodeGen/TargetLoweringBase.cpp 672 setOperationAction(ISD::ADDC, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 298 setOperationAction(ISD::ADDC, MVT::i32, Custom);
302 setOperationAction(ISD::ADDC, MVT::i64, Custom);
2326 case ISD::ADDC:
2996 case ISD::ADDC:
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 739 case ISD::ADDC:
987 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC;
988 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE;
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 326 setOperationAction(ISD::ADDC, VT, Legal);
lib/Target/AMDGPU/R600ISelLowering.cpp 258 setOperationAction(ISD::ADDC, VT, Expand);
lib/Target/AVR/AVRISelLowering.cpp 68 setOperationAction(ISD::ADDC, VT, Legal);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 213 if (Opc == ISD::ADDC) {
lib/Target/Mips/MipsSEISelLowering.cpp 108 setOperationAction(ISD::ADDC, MVT::i32, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 192 setOperationAction(ISD::ADDC, VT, Legal);
15238 SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
lib/Target/Sparc/SparcISelLowering.cpp 1548 setOperationAction(ISD::ADDC, MVT::i32, Custom);
1554 setOperationAction(ISD::ADDC, MVT::i64, Custom);
2904 case ISD::ADDC: hiOpc = ISD::ADDE; break;
3052 case ISD::ADDC:
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 114 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {