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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc99232 /*223624*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->223641
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63019 /*137476*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::BR),// ->137503
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 8875 /* 34028*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->34045
gen/lib/Target/ARC/ARCGenDAGISel.inc 995 /* 1682*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->1699
gen/lib/Target/ARM/ARMGenDAGISel.inc37797 /* 83234*/ /*SwitchOpcode*/ 55, TARGET_VAL(ISD::BR),// ->83292
gen/lib/Target/AVR/AVRGenDAGISel.inc 1258 /* 2177*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->2194
gen/lib/Target/BPF/BPFGenDAGISel.inc 1768 /* 3078*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->3095
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc67987 /*131524*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::BR),// ->131542
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 1232 /* 2248*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->2265
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 4589 /* 9146*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->9163
gen/lib/Target/Mips/MipsGenDAGISel.inc24188 /* 45345*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::BR),// ->45417
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc69502 /*146872*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->146889
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28058 /* 67681*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->67698
gen/lib/Target/RISCV/RISCVGenDAGISel.inc11875 /* 22102*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->22119
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2897 /* 5353*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->5370
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc21320 /* 40071*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->40088
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc16575 /* 32169*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->32186
gen/lib/Target/X86/X86GenDAGISel.inc58133 /*122785*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->122802
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2183 /* 3816*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->3833
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 1608 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2235 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2321 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(),
2396 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2458 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
2465 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo,
2584 SDValue Br = DAG.getNode(ISD::BR, dl,
2674 Root = DAG.getNode(ISD::BR, dl, MVT::Other, Root, DAG.getBasicBlock(MBB));
2733 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2821 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(),
2850 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
10101 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
10526 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 346 case ISD::BR: return "br";
lib/Target/AMDGPU/SIISelLowering.cpp 4450 BR = findUser(BRCOND, ISD::BR);
4503 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
lib/Target/ARM/ARMISelLowering.cpp14145 assert((N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BR)
14153 SDValue NewBr = DAG.getNode(ISD::BR, SDLoc(Br), MVT::Other, NewBrOps);
lib/Target/PowerPC/PPCISelLowering.cpp14042 return DAG.getNode(ISD::BR, dl, MVT::Other,
lib/Target/X86/X86ISelLowering.cpp22080 if (User->getOpcode() == ISD::BR) {
22121 if (User->getOpcode() == ISD::BR) {