reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

50588 /*108842*/        OPC_CheckChild2CondCode, ISD::SETOLT,
50616 /*108918*/        OPC_CheckChild2CondCode, ISD::SETOLT,
51090 /*110211*/        OPC_CheckChild2CondCode, ISD::SETOLT,
51118 /*110287*/        OPC_CheckChild2CondCode, ISD::SETOLT,
51592 /*111580*/        OPC_CheckChild2CondCode, ISD::SETOLT,
51620 /*111656*/        OPC_CheckChild2CondCode, ISD::SETOLT,
60915 /*133084*/        OPC_CheckChild2CondCode, ISD::SETOLT,
61372 /*134181*/        OPC_CheckChild2CondCode, ISD::SETOLT,
61830 /*135280*/        OPC_CheckChild2CondCode, ISD::SETOLT,

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

30294 /* 58499*/          OPC_CheckChild2CondCode, ISD::SETOLT,
30449 /* 58845*/          OPC_CheckChild2CondCode, ISD::SETOLT,
51980 /* 97970*/          OPC_CheckChild2CondCode, ISD::SETOLT,

gen/lib/Target/Mips/MipsGenDAGISel.inc

17147 /* 32020*/        OPC_CheckChild2CondCode, ISD::SETOLT,
17231 /* 32176*/        OPC_CheckChild2CondCode, ISD::SETOLT,
17400 /* 32533*/        OPC_CheckChild2CondCode, ISD::SETOLT,
17484 /* 32689*/        OPC_CheckChild2CondCode, ISD::SETOLT,
17966 /* 33649*/        OPC_CheckChild2CondCode, ISD::SETOLT,
18069 /* 33840*/        OPC_CheckChild2CondCode, ISD::SETOLT,

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

60920 /*128890*/      OPC_CheckChild2CondCode, ISD::SETOLT,
60944 /*128938*/      OPC_CheckChild2CondCode, ISD::SETOLT,
60968 /*128986*/      OPC_CheckChild2CondCode, ISD::SETOLT,
60982 /*129013*/      OPC_CheckChild2CondCode, ISD::SETOLT,
60996 /*129040*/      OPC_CheckChild2CondCode, ISD::SETOLT,
61020 /*129088*/      OPC_CheckChild2CondCode, ISD::SETOLT,
61044 /*129136*/      OPC_CheckChild2CondCode, ISD::SETOLT,
61058 /*129163*/      OPC_CheckChild2CondCode, ISD::SETOLT,
63924 /*134846*/      OPC_CheckChild2CondCode, ISD::SETOLT,
63953 /*134910*/      OPC_CheckChild2CondCode, ISD::SETOLT,
63982 /*134974*/      OPC_CheckChild2CondCode, ISD::SETOLT,
64011 /*135038*/      OPC_CheckChild2CondCode, ISD::SETOLT,
66768 /*141133*/        OPC_CheckChild2CondCode, ISD::SETOLT,
67470 /*142636*/        OPC_CheckChild2CondCode, ISD::SETOLT,
68116 /*144025*/        OPC_CheckChild2CondCode, ISD::SETOLT,

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

25974 /* 62699*/        OPC_CheckChild2CondCode, ISD::SETOLT,
26044 /* 62867*/        OPC_CheckChild2CondCode, ISD::SETOLT,
26330 /* 63683*/        OPC_CheckChild2CondCode, ISD::SETOLT,
26400 /* 63851*/        OPC_CheckChild2CondCode, ISD::SETOLT,
26686 /* 64667*/        OPC_CheckChild2CondCode, ISD::SETOLT,
26887 /* 65214*/        OPC_CheckChild2CondCode, ISD::SETOLT,
27097 /* 65743*/        OPC_CheckChild2CondCode, ISD::SETOLT,

gen/lib/Target/RISCV/RISCVGenDAGISel.inc

 7233 /* 13463*/        OPC_CheckChild2CondCode, ISD::SETOLT,
 7454 /* 13943*/        OPC_CheckChild2CondCode, ISD::SETOLT,

gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc

 7741 /* 14351*/            OPC_CheckChild2CondCode, ISD::SETOLT,
 7817 /* 14490*/            OPC_CheckChild2CondCode, ISD::SETOLT,
 8119 /* 15051*/            OPC_CheckChild2CondCode, ISD::SETOLT,
 8202 /* 15204*/          OPC_CheckChild2CondCode, ISD::SETOLT,

lib/CodeGen/Analysis.cpp

  207   case FCmpInst::FCMP_OLT:   return ISD::SETOLT;
  227     case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT;

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 8140   case ISD::SETOLT:
12289       case ISD::SETOLT:
19742           Sqrt.getOperand(0) == CmpLHS && (CC == ISD::SETOLT ||

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1683     case ISD::SETOLT:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  423     case ISD::SETOLT: Result = ISD::SETULT  ; break;  // SETULT & SETNE
 1983   case ISD::SETOLT:
 2056     case ISD::SETOLT: return getBoolConstant(R==APFloat::cmpLessThan, dl, VT,

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  402     case ISD::SETOLT:                   return "setolt";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

  306   case ISD::SETOLT:
 3749             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);

lib/Target/AArch64/AArch64ISelLowering.cpp

 1475   case ISD::SETOLT:

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 1290   case ISD::SETOLT:
 2275   SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);

lib/Target/AMDGPU/R600ISelLowering.cpp

  126   setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);

lib/Target/AMDGPU/SIInsertSkips.cpp

  207     case ISD::SETOLT:

lib/Target/ARM/ARMISelLowering.cpp

 1825   case ISD::SETOLT: CondCode = ARMCC::MI; break;
 4619   else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
 4625   if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
 6222     case ISD::SETOLT:

lib/Target/Lanai/LanaiISelLowering.cpp

  854   case ISD::SETOLT:

lib/Target/Mips/MipsISelLowering.cpp

  611   case ISD::SETOLT: return Mips::FCOND_OLT;

lib/Target/Mips/MipsSEISelLowering.cpp

 1835                         Op->getOperand(2), ISD::SETOLT);

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

  548     case ISD::SETOLT:

lib/Target/NVPTX/NVPTXISelLowering.cpp

 2127                                 DAG.getConstantFP(0.5, SL, VT), ISD::SETOLT);
 2153                                 DAG.getConstantFP(0.5, SL, VT), ISD::SETOLT);

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 3783         case ISD::SETOLT:
 3810         case ISD::SETOLT:
 3847   case ISD::SETOLT:
 3870   case ISD::SETOLT:
 3909       case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;

lib/Target/PowerPC/PPCISelLowering.cpp

 7253     case ISD::SETOLT:

lib/Target/Sparc/SparcISelLowering.cpp

 1390   case ISD::SETOLT: return SPCC::FCC_L;

lib/Target/SystemZ/SystemZISelLowering.cpp

 1947   CONV(LT);

lib/Target/X86/X86ISelLowering.cpp

 4724   case ISD::SETOLT:
 4742   case ISD::SETOLT:              // flipped
20465   case ISD::SETOLT: SSECC = 1; break;
36874       case ISD::SETOLT:
36972       case ISD::SETOLT: