reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

61032 /*133370*/        OPC_CheckChild2CondCode, ISD::SETUO,
61489 /*134467*/        OPC_CheckChild2CondCode, ISD::SETUO,
61960 /*135592*/        OPC_CheckChild2CondCode, ISD::SETUO,

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

30318 /* 58543*/          OPC_CheckChild2CondCode, ISD::SETUO,
30473 /* 58889*/          OPC_CheckChild2CondCode, ISD::SETUO,

gen/lib/Target/Mips/MipsGenDAGISel.inc

17126 /* 31981*/        OPC_CheckChild2CondCode, ISD::SETUO,
17210 /* 32137*/        OPC_CheckChild2CondCode, ISD::SETUO,
17379 /* 32494*/        OPC_CheckChild2CondCode, ISD::SETUO,
17463 /* 32650*/        OPC_CheckChild2CondCode, ISD::SETUO,
18008 /* 33727*/        OPC_CheckChild2CondCode, ISD::SETUO,
18111 /* 33918*/        OPC_CheckChild2CondCode, ISD::SETUO,

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

63656 /*134290*/      OPC_CheckChild2CondCode, ISD::SETUO,
63680 /*134338*/      OPC_CheckChild2CondCode, ISD::SETUO,
63704 /*134386*/      OPC_CheckChild2CondCode, ISD::SETUO,
63718 /*134413*/      OPC_CheckChild2CondCode, ISD::SETUO,
63732 /*134440*/      OPC_CheckChild2CondCode, ISD::SETUO,
63756 /*134488*/      OPC_CheckChild2CondCode, ISD::SETUO,
63780 /*134536*/      OPC_CheckChild2CondCode, ISD::SETUO,
63794 /*134563*/      OPC_CheckChild2CondCode, ISD::SETUO,
66012 /*139454*/      OPC_CheckChild2CondCode, ISD::SETUO,
66041 /*139518*/      OPC_CheckChild2CondCode, ISD::SETUO,
66070 /*139582*/      OPC_CheckChild2CondCode, ISD::SETUO,
66099 /*139646*/      OPC_CheckChild2CondCode, ISD::SETUO,
67398 /*142483*/        OPC_CheckChild2CondCode, ISD::SETUO,
68064 /*143914*/        OPC_CheckChild2CondCode, ISD::SETUO,
68386 /*144619*/        OPC_CheckChild2CondCode, ISD::SETUO,

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

26034 /* 62843*/        OPC_CheckChild2CondCode, ISD::SETUO,
26390 /* 63827*/        OPC_CheckChild2CondCode, ISD::SETUO,
26746 /* 64811*/        OPC_CheckChild2CondCode, ISD::SETUO,
26880 /* 65201*/        OPC_CheckChild2CondCode, ISD::SETUO,
27090 /* 65730*/        OPC_CheckChild2CondCode, ISD::SETUO,

gen/lib/Target/RISCV/RISCVGenDAGISel.inc

 7337 /* 13683*/        OPC_CheckChild2CondCode, ISD::SETUO,
 7558 /* 14163*/        OPC_CheckChild2CondCode, ISD::SETUO,

lib/CodeGen/Analysis.cpp

  211   case FCmpInst::FCMP_UNO:   return ISD::SETUO;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1676     case ISD::SETUO:
 1696           CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
 1715     if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  420     case ISD::SETUO : Result = ISD::SETFALSE; break;  // SETUGT & SETULT
 1987   case ISD::SETUO:
 2076     case ISD::SETUO:  return getBoolConstant(R==APFloat::cmpUnordered, dl, VT,

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  407     case ISD::SETUO:                    return "setuo";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

  323   case ISD::SETUO:
 3704     if (Cond == ISD::SETO || Cond == ISD::SETUO)
 3769     ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;

lib/Target/AArch64/AArch64ISelLowering.cpp

 1488   case ISD::SETUO:
 1559   case ISD::SETUO:

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 1280   case ISD::SETUO:

lib/Target/AMDGPU/R600ISelLowering.cpp

  123   setCondCodeAction(ISD::SETUO,  MVT::f32, Expand);

lib/Target/AMDGPU/SIISelLowering.cpp

 8339     if ((LCC == ISD::SETO || LCC == ISD::SETUO) && Mask &&

lib/Target/AMDGPU/SIInsertSkips.cpp

  222     case ISD::SETUO:

lib/Target/ARM/ARMISelLowering.cpp

 1829   case ISD::SETUO:  CondCode = ARMCC::VS; break;
 6246     case ISD::SETUO: Invert = true; LLVM_FALLTHROUGH;

lib/Target/Lanai/LanaiISelLowering.cpp

  859   case ISD::SETUO:

lib/Target/Mips/MipsISelLowering.cpp

  622   case ISD::SETUO:  return Mips::FCOND_UN;

lib/Target/Mips/MipsSEISelLowering.cpp

 1859                         Op->getOperand(2), ISD::SETUO);

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

  556     case ISD::SETUO:

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 3856   case ISD::SETUO:  return PPC::PRED_UN;
 3876   case ISD::SETUO:  return 3;                  // Bit #3 = SETUO

lib/Target/PowerPC/PPCISelLowering.cpp

  484     setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
  485     setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
  742     setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
  781       setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);

lib/Target/Sparc/SparcISelLowering.cpp

 1401   case ISD::SETUO:  return SPCC::FCC_U;

lib/Target/SystemZ/SystemZISelLowering.cpp

 1951   case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
 2690   case ISD::SETUO:

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

   88     for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,

lib/Target/X86/X86ISelLowering.cpp

 4756   case ISD::SETUO:   return X86::COND_P;
20470   case ISD::SETUO:  SSECC = 3; break;
41970   SDValue IsOp0Nan = DAG.getSetCC(DL, SetCCType, Op0, Op0, ISD::SETUO);