reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

60229 /*131794*/  /*SwitchOpcode*/ 30, TARGET_VAL(ISD::SUBE),// ->131827

gen/lib/Target/AVR/AVRGenDAGISel.inc

  808 /*  1345*/  /*SwitchOpcode*/ 63, TARGET_VAL(ISD::SUBE),// ->1411

gen/lib/Target/Lanai/LanaiGenDAGISel.inc

  808 /*  1430*/  /*SwitchOpcode*/ 73, TARGET_VAL(ISD::SUBE),// ->1506

gen/lib/Target/MSP430/MSP430GenDAGISel.inc

 1699 /*  3517*/      /*SwitchOpcode*/ 21|128,2/*277*/, TARGET_VAL(ISD::SUBE),// ->3798
 4052 /*  8154*/  /*SwitchOpcode*/ 23|128,1/*151*/, TARGET_VAL(ISD::SUBE),// ->8309

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

57929 /*123167*/  /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SUBE),// ->123204

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

24411 /* 59127*/  /*SwitchOpcode*/ 91, TARGET_VAL(ISD::SUBE),// ->59221

gen/lib/Target/Sparc/SparcGenDAGISel.inc

 2293 /*  4219*/  /*SwitchOpcode*/ 36, TARGET_VAL(ISD::SUBE),// ->4258

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1507   case ISD::SUBE:               return visitSUBE(N);

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  147   case ISD::SUBE:
 1770   case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
 2173       Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
 2270     Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  295   case ISD::SUBE:                       return "sube";

lib/CodeGen/TargetLoweringBase.cpp

  675     setOperationAction(ISD::SUBE, VT, Expand);

lib/Target/AArch64/AArch64ISelLowering.cpp

  301   setOperationAction(ISD::SUBE, MVT::i32, Custom);
  305   setOperationAction(ISD::SUBE, MVT::i64, Custom);
 2336   case ISD::SUBE:
 2999   case ISD::SUBE:

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  742   case ISD::SUBE: {
  985   bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  329     setOperationAction(ISD::SUBE, VT, Legal);

lib/Target/AMDGPU/R600ISelLowering.cpp

  261     setOperationAction(ISD::SUBE, VT, Expand);

lib/Target/AVR/AVRISelLowering.cpp

   71     setOperationAction(ISD::SUBE, VT, Legal);

lib/Target/Lanai/LanaiAluCode.h

  126   case ISD::SUBE:

lib/Target/PowerPC/PPCISelLowering.cpp

  195     setOperationAction(ISD::SUBE, VT, Legal);

lib/Target/Sparc/SparcISelLowering.cpp

 1551   setOperationAction(ISD::SUBE, MVT::i32, Custom);
 1557     setOperationAction(ISD::SUBE, MVT::i64, Custom);
 2906   case ISD::SUBC: hiOpc = ISD::SUBE; break;
 2907   case ISD::SUBE: hasChain = true; break;
 3055   case ISD::SUBE:               return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  114         ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {