reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

   79   MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));

lib/CodeGen/MachineInstr.cpp

 2021   auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
 2040   auto MIB = BuildMI(MF, DL, MCID).add(MO);

lib/CodeGen/MachineInstrBundle.cpp

  135       BuildMI(MF, getDebugLoc(FirstMI, LastMI), TII->get(TargetOpcode::BUNDLE));

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  691     auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
  702     auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
  713   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
  772   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
  845   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
 1055         BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));

lib/CodeGen/TargetLoweringBase.cpp

 1046     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
 1105   auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
 1120   auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());

lib/Target/AArch64/AArch64FrameLowering.cpp

  505     MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFRegP_X))
  519       MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFPLR_X))
  523       MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveRegP_X))
  535     MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFReg_X))
  546     MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveReg_X))
  556     MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFRegP))
  568       MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFPLR))
  572       MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveRegP))
  582     MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveReg))
  591     MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFReg))

lib/Target/AArch64/AArch64InstrInfo.cpp

 5545     MachineInstr *TC = BuildMI(MF, DebugLoc(), get(TailOpcode))
 5574     MachineInstr *STRXpre = BuildMI(MF, DebugLoc(), get(AArch64::STRXpre))
 5601     MachineInstr *LDRXpost = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost))
 5615   MachineInstr *ret = BuildMI(MF, DebugLoc(), get(AArch64::RET))
 5635     It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::TCRETURNdi))
 5645     It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::BL))
 5675     Save = BuildMI(MF, DebugLoc(), get(AArch64::STRXpre))
 5680     Restore = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost))
 5691   It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::BL))

lib/Target/AMDGPU/SIInstrInfo.cpp

 6081         BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_END_CF))
 6126         BuildMI(*(MF), Branch->getDebugLoc(), get(AMDGPU::SI_LOOP))

lib/Target/ARM/ARMBaseInstrInfo.cpp

  247       MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
  263       MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))

lib/Target/ARM/Thumb1FrameLowering.cpp

  892     MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH))
 1022       BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));

lib/Target/Hexagon/HexagonStoreWidening.cpp

  434         BuildMI(*MF, DL, StD)
  457         BuildMI(*MF, DL, StD)

lib/Target/Mips/MipsBranchExpansion.cpp

  485           BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
  596           BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
  667           .append(BuildMI(*MFp, DL, TII->get(Mips::J)).addMBB(TgtMBB))
  668           .append(BuildMI(*MFp, DL, TII->get(Mips::NOP)));
  762               BuildMI(*MFp, I->getDebugLoc(), TII->get(Mips::NOP)));

lib/Target/PowerPC/PPCFrameLowering.cpp

 2249         MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))

lib/Target/PowerPC/PPCInstrInfo.cpp

  427     return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
 1210       BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),

lib/Target/X86/X86ISelLowering.cpp

30209     BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0).addImm(0);
30217     BuildMI(MF, DL, TII.get(AdjStackUp)).addImm(0).addImm(0);

lib/Target/X86/X86InstrInfo.cpp

  933     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
  958         BuildMI(MF, MI.getDebugLoc(), get(Opc))
  994         BuildMI(MF, MI.getDebugLoc(), get(Opc))
 1016     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
 1059     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
 1083         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
 1100     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
 1141     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
 1161     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
 1242     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
 1307     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
 5585     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
 8114   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
 8127                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
 8132                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))

lib/Target/XCore/XCoreFrameLowering.cpp

  518         New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode)).addImm(Amount);