reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

  637   auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg)

 1689     MachineInstr *NI = BuildMI(NewBB, DebugLoc(), TII->get(TargetOpcode::PHI), R)

  287           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);

  201     BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
  203   BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
  205   BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
  219   BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg)
  286   BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
  290   BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
  294   BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
  298   BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
  311   BuildMI(StoreBB, DL, TII->get(AArch64::STLXPX), StatusReg)

  968   MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
  991   MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
 1113   MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);

 2382     BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
 2386     BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
 2394     BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)
 2400     BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
 2415     BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
 2420     BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
 2427     BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
 2441     BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
 2469     BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)
 2474     BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
 2482     BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)
 2487     BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
 2533       BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)

 9573     BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
 9586       BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
 9593         BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
 9611     BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT), NewVReg3)
 9616     BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
 9629     BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
 9668     BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
 9675     BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
 9680     BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
 9690     BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
 9699       BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
 9711     BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
 9724       BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
 9731         BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
 9770     BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
 9776     BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
 9783     BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
10134     BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi16 : ARM::MOVi16), Vtmp)
10139       BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVTi16 : ARM::MOVTi16), varEnd)
10189   BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
10192   BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)

 1537   BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
 1542   BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
 1548   auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
 1552   BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)

  576   BuildMI(BB, DL, TII.get(BPF::MOV_32_64), PromotedReg0).addReg(Reg);
  577   BuildMI(BB, DL, TII.get(BPF::SLL_ri), PromotedReg1)
  579   BuildMI(BB, DL, TII.get(RShiftOp), PromotedReg2)

 1273   BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)

  711       MachineInstr *NewCmp = BuildMI(&MBB, DL,

 1507   BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
 1510   BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
 1514     BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
 1517     BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
 1521     BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
 1523   BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)

  145   BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0);
  146   BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2)
  157   BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch)
  160   BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch)
  163   BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
  175   BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
  179     BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
  183     BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
  186     BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
  278   BuildMI(loop1MBB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
  286   BuildMI(loop2MBB, DL, TII->get(MOVE), Scratch).addReg(NewVal).addReg(ZERO);
  287   BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
  404   BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
  409     BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
  412     BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes)
  415     BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
  421     BuildMI(loopMBB, DL, TII->get(Opcode), BinOpRes)
  424     BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
  429     BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
  438   BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
  440   BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
  442   BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
  454   BuildMI(sinkMBB, DL, TII->get(Mips::AND), Dest)
  456   BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
  460     BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
  463     BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
  466     BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
  592   BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
  596     BuildMI(loopMBB, DL, TII->get(Opcode), Scratch).addReg(OldVal).addReg(Incr);
  600     BuildMI(loopMBB, DL, TII->get(AND), Scratch).addReg(OldVal).addReg(Incr);
  601     BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch);
  604     BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
  607   BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);

 1545     BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
 1550     BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
 1562   BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
 1563   BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
 1670   BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
 1672   BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
 1674   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
 1677     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
 1680     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
 1682     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
 1684   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
 1686   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
 1688   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
 1689   BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
 1851   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
 1853   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
 1855   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
 1858     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
 1861     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
 1863     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
 1865   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
 1867   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
 1869   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
 1870   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
 1872   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
 1874   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
 1876   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)

10381   BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
10384     BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
10389       BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH),
10391       BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
10394       BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
10504     BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
10512   BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
10518     BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg)
10522     BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
10527     BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
10532   BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg);
10534     BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
10536     BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
10537     BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
10541   BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
10546   BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
10550     BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
10553   BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg)
10556   BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg);
10561     BuildMI(BB, dl, TII->get(PPC::AND), SReg)
10568       BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg)
10572       BuildMI(BB, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueSReg)
10577     BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
10588   BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg).addReg(Tmp3Reg).addReg(Tmp2Reg);
10721       BuildMI(mainMBB, DL,
10738   BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
11028     BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
11029     BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
11030     BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
11034     BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
11210     BuildMI(BB, dl, TII->get(LoadMnemonic), dest).addReg(ptrA).addReg(ptrB);
11211     BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
11328       BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
11337     BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
11343       BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg)
11347       BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
11352       BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
11357     BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
11360     BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
11364       BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
11366       BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
11367       BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
11371     BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
11374     BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
11377     BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
11382     BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
11385     BuildMI(BB, dl, TII->get(PPC::AND), TmpReg)
11388     BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
11399     BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg)
11402     BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg)

  250   BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
  256     BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
  259     BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
  264   BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
  284   BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg)
  287   BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg)
  290   BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg)
  316   BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
  322     BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
  327     BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
  332     BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg)
  337     BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
  340     BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
  349   BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg)
  399   BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg)
  402   BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg)
  456   BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
  458   BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg)
  461   BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg)
  508   BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg)
  564     BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
  573     BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
  586     BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
  588     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg)
  604     BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
  643   BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
  645   BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg)

 1128   BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg)
 1131   BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg)
 1134   BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), ReadAgainReg)

 6856   BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
 6868   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
 6872     BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
 6877     BuildMI(MBB, DL, TII->get(BinOpcode), Tmp).addReg(RotatedOldVal).add(Src2);
 6880       BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
 6886       BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
 6887       BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
 6892     BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
 6898     BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
 6902     BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
 6904   BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
 6976   BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
 6985   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
 6989     BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
 7003     BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
 7016   BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
 7020     BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
 7022   BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
 7086   BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
 7107   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
 7110   BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
 7113   BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
 7116   BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
 7118   BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
 7138   BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
 7140   BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
 7142   BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
 7285     BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
 7289       BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
 7292     BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
 7321     BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
 7324       BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
 7326     BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
 7439   BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
 7442   BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
 7445   BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);

 1140       BuildMI(NestedEHPad, RangeEnd->getDebugLoc(), TII.get(WebAssembly::CATCH),

  442       BuildMI(Routing, DebugLoc(), TII.get(WebAssembly::CONST_I32), Reg)

  388     BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg);
  390   BuildMI(BB, DL, TII.get(FConst), Tmp1)
  392   BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1);
  400     BuildMI(BB, DL, TII.get(FConst), Tmp1)
  402     BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1);
  403     BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg);
  407   BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg);
  412   BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg);
  414   BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute);

  345       BuildMI(ElseMBB, DL, TII.get(WebAssembly::CONST_I32), Reg).addImm(0);

  644     BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
  649   BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
  652   BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
  653   BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
  656   BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg)
  668   BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
  680   BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
  689     BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
  697   addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
 2378       BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
 2405       BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
 2438       BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
 2447         BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
 2468       BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
 2470     BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
 2472     BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
 2690     addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
 2700     addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),

29227   BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), mainDstReg).addImm(-1);
29236   BuildMI(fallMBB, DL, TII->get(TargetOpcode::COPY), fallDstReg)
29381     BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
29406     BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
29416     BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
29422     BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
29428     BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
29453   BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
29469     BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
29473     BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
29477     BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
29484   BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
30072   BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
30073   BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
30082   BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
30084   BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
30092     BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
30100     BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
30108     BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
30118     BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
30121   BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
30589   BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
30607     addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
30611   BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
30697   BuildMI(checkSspMBB, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg);
30714       BuildMI(fallMBB, DL, TII->get(PtrLoadOpc), PrevSSPReg);
30730   BuildMI(fallMBB, DL, TII->get(SubRROpc), SspSubReg)
30743   BuildMI(fixShadowMBB, DL, TII->get(ShrRIOpc), SspFirstShrReg)
30753   BuildMI(fixShadowMBB, DL, TII->get(ShrRIOpc), SspSecondShrReg)
30765   BuildMI(fixShadowLoopPrepareMBB, DL, TII->get(ShlR1Opc), SspAfterShlReg)
30771   BuildMI(fixShadowLoopPrepareMBB, DL, TII->get(MovRIOpc), Value128InReg)
30779   BuildMI(fixShadowLoopMBB, DL, TII->get(X86::PHI), CounterReg)
30790   BuildMI(fixShadowLoopMBB, DL, TII->get(DecROpc), DecReg).addReg(CounterReg);
31023     addRegOffset(BuildMI(DispatchBB, DL, TII->get(Op), BP), FP, true,
31033   addFrameReference(BuildMI(DispatchBB, DL, TII->get(X86::MOV32rm), IReg), FI,
31045     BuildMI(DispContBB, DL, TII->get(X86::LEA64r), BReg)
31052     BuildMI(DispContBB, DL, TII->get(TargetOpcode::SUBREG_TO_REG), IReg64)
31073       BuildMI(DispContBB, DL, TII->get(X86::MOV32rm), OReg)
31080       BuildMI(DispContBB, DL, TII->get(X86::MOVSX64rr32), OReg64).addReg(OReg);
31082       BuildMI(DispContBB, DL, TII->get(X86::ADD64rr), TReg)