|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/CodeGen/ModuloSchedule.cpp 812 BuildMI(*KernelBB, MI, MI->getDebugLoc(),
lib/CodeGen/PeepholeOptimizer.cpp 585 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
766 MachineInstrBuilder MIB = BuildMI(*MBB, &OrigPHI, OrigPHI.getDebugLoc(),
1235 BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
lib/CodeGen/TwoAddressInstructionPass.cpp 1552 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 770 BuildMI(*MBB, &MI, DL, TII->get(AArch64::ORRXrs), ScratchReg)
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 136 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
226 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
313 BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
332 = BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
357 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
360 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
366 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_I32_e64), DstLo)
371 MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi)
382 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
419 BuildMI(*BB, &I, DL, TII.get(NewOpc), Dst0Reg)
422 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), Dst1Reg)
445 MachineInstr *Copy = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY),
480 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::REG_SEQUENCE), DstReg);
528 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
604 BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG), DstReg)
733 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg)
746 MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode),
1062 BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef);
1104 MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1112 MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg)
1127 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1439 ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B64), DstReg)
1447 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
1450 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)
1453 ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
1546 BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1591 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CondPhysReg)
1641 BuildMI(*BB, &I, DL, TII.get(MovOpc), ImmReg)
1645 BuildMI(*BB, &I, DL, TII.get(NewOpc), DstReg)
1656 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg)
1658 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg)
1661 BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskLo)
1664 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
1941 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
2013 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::V_MOV_B32_e32),
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 1027 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 300 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY),
309 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(Opc),
lib/Target/AMDGPU/SIFoldOperands.cpp 263 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg())
708 BuildMI(MBB, UseMI, DL,
735 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);
746 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);
750 BuildMI(MBB, UseMI, DL,
lib/Target/AMDGPU/SIISelLowering.cpp 3654 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64),
3662 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
3704 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFE_U32), CountReg)
3707 BuildMI(*BB, FirstMI, DebugLoc(),
3715 BuildMI(*BB, FirstMI, DebugLoc(),
lib/Target/AMDGPU/SIInsertSkips.cpp 287 BuildMI(MBB, &MI, DL, TII->get(ST.isWave32() ? AMDGPU::S_MOV_B32
296 BuildMI(MBB, &MI, DL, TII->get(Opcode), Exec)
lib/Target/AMDGPU/SIInstrInfo.cpp 4802 BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
lib/Target/AMDGPU/SILowerControlFlow.cpp 375 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), Dst)
378 Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
382 Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
400 BuildMI(MBB, &MI, DL, TII->get(Andn2TermOpc), Exec)
lib/Target/AMDGPU/SIWholeQuadMode.cpp 845 BuildMI(*MI->getParent(), MI, DL, TII->get(AMDGPU::COPY), Dest)
lib/Target/ARM/MLxExpansionPass.cpp 290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
lib/Target/Hexagon/HexagonBitSimplify.cpp 2064 BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR)
lib/Target/Hexagon/HexagonFrameLowering.cpp 2356 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2361 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2367 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2371 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2377 BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2382 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
lib/Target/Hexagon/HexagonGenPredicate.cpp 422 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
436 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR)
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1592 BuildMI(B, DI, DL, TII->get(DI->getOpcode()), NewR).addImm(Val);
lib/Target/Hexagon/HexagonInstrInfo.cpp 743 BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
lib/Target/Hexagon/HexagonSplitDouble.cpp 652 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first)
655 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second)
679 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR)
721 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
723 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
741 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
744 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second)
749 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
752 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
770 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
772 BuildMI(B, MI, DL, TII->get(Hexagon::S2_asr_i_r), P.second)
810 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
812 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), HiR)
835 BuildMI(B, MI, DL, TII->get(A2_aslh), LoR)
838 BuildMI(B, MI, DL, TII->get(A2_asrh), TmpR)
841 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR))
847 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR)
852 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
858 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR)
862 BuildMI(B, MI, DL, TII->get(S2_insert), LoR)
869 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), (Left ? HiR : LoR))
872 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
875 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
881 BuildMI(B, MI, DL, TII->get(A2_aslh), HiR)
884 BuildMI(B, MI, DL, TII->get(A2_asrh), LoR)
887 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR))
892 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
896 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
945 BuildMI(B, MI, DL, TII->get(A2_or), LoR)
948 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
952 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), LoR)
957 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1)
962 BuildMI(B, MI, DL, TII->get(A2_or), TmpR2)
965 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
974 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
976 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
985 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
987 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
1117 BuildMI(B, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), NewDR)
lib/Target/Hexagon/HexagonVExtract.cpp 82 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR)
90 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR)
93 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L4_loadri_rr), ElemR)
148 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::PS_fi), BaseR)
lib/Target/NVPTX/NVPTXFrameLowering.cpp 55 MI = BuildMI(MBB, MI, dl,
60 BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode),
lib/Target/PowerPC/PPCMIPeephole.cpp 372 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
393 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
418 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
474 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
656 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
658 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
705 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
795 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
1440 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 951 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
lib/Target/SystemZ/SystemZInstrInfo.cpp 221 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
226 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
232 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
lib/Target/SystemZ/SystemZLDCleanup.cpp 119 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
139 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
lib/Target/SystemZ/SystemZPostRewrite.cpp 228 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(SystemZ::COPY), DstReg)
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 249 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc), NewReg)
259 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc),
351 BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc), NewReg)
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 192 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp)
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 126 MachineInstr *Const = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
613 MachineInstr *Tee = BuildMI(MBB, Insert, Insert->getDebugLoc(),
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 397 BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode),
lib/Target/X86/X86CallFrameOptimization.cpp 544 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg);
545 BuildMI(MBB, Context.Call, DL, TII->get(X86::INSERT_SUBREG), Reg)
lib/Target/X86/X86DomainReassignment.cpp 188 MachineInstrBuilder Bld = BuildMI(*MBB, MI, DL, TII->get(DstOpcode), Reg);
lib/Target/X86/X86FixupSetCC.cpp 143 BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
148 BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
lib/Target/X86/X86InstrInfo.cpp 850 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
3913 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
7934 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
lib/Target/X86/X86WinAllocaExpander.cpp 248 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA)