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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/MachineInstrBuilder.h 410 return BuildMI(BB, *I, DL, MCID);
lib/CodeGen/TwoAddressInstructionPass.cpp 1837 MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/CodeGen/XRayInstrumentation.cpp 108 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc))
139 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc));
205 BuildMI(FirstMBB, FirstMI, FirstMI.getDebugLoc(),
lib/Target/AArch64/AArch64CondBrTuning.cpp 137 return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 291 BuildMI(*MBB, BrMI, BrMI.getDebugLoc(), TII->get(AArch64::Bcc))
lib/Target/AArch64/AArch64InstrInfo.cpp 1513 BuildMI(MBB, MI, DL, get(AArch64::LDRWui))
1555 BuildMI(MBB, MI, DL, get(AArch64::LDRWui))
4835 MachineInstr *NewMI = BuildMI(RefToMBB, MI, DL, get(Opc))
4875 BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB);
lib/Target/AArch64/AArch64InstructionSelector.cpp 1000 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CBOpc))
1096 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::ADDXri))
1104 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::STRXui))
1416 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
1424 auto CMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
1430 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::Bcc))
2047 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
2173 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
2178 MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc))
2229 auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
2244 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
2253 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
2259 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
2751 MachineInstr &SubRegMI = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
2759 MachineInstr &SubRegMI2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
2766 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri))
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 569 BuildMI(MBB, MI, DL, *ReplInstrMCID[2])
609 BuildMI(MBB, MI, DL, *ReplInstrMCID[8])
614 BuildMI(MBB, MI, DL, *ReplInstrMCID[9])
lib/Target/AMDGPU/GCNDPPCombine.cpp 167 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
lib/Target/AMDGPU/SIISelLowering.cpp 3727 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
3790 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
lib/Target/AMDGPU/SIInstrInfo.cpp 1488 BuildMI(MBB, MI, DL, MovRelDesc)
1577 auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
2663 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2674 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2684 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2697 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
3062 BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32));
4758 BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4788 Addr64 = BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 924 auto NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(Opc));
930 auto NewInst = BuildMI(MBB, MISucc, MISucc.getDebugLoc(), TII->get(SuccOpc));
1010 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), SDWADesc);
lib/Target/ARC/ARCExpandPseudos.cpp 68 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(),
lib/Target/ARM/ARMISelLowering.cpp 9394 BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
9433 BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
9455 BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
10158 BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci))
10164 BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp))
10289 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
10305 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
10348 BuildMI(*MBB, MI, DL, TII->get(ARM::tCMPi8))
10352 BuildMI(*MBB, MI, DL, TII->get(ARM::t2Bcc))
10412 BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
10448 BuildMI(*BB, MI, dl, TII->get(NewOpc))
10469 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
lib/Target/ARM/ARMInstructionSelector.cpp 1141 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri))
1150 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc))
lib/Target/Hexagon/HexagonInstrInfo.cpp 1034 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1098 MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc))
1104 BuildMI(MBB, MI, DL, get(NewOpc))
1266 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1275 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1302 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1314 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1442 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1446 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1454 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1458 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1466 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1470 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1478 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1483 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1491 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1496 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1504 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1509 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1579 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
lib/Target/Mips/Mips16ISelLowering.cpp 714 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
717 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
739 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
740 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
764 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
784 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
lib/Target/Mips/MipsInstructionSelector.cpp 245 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
269 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
276 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
286 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
298 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
305 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
318 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL))
326 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
335 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
347 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
357 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
366 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
413 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
429 PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(),
437 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(),
449 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
457 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
517 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
536 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
542 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
554 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
578 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
589 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
597 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
610 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
620 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
757 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
766 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode))
773 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode))
785 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
794 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu))
801 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW))
lib/Target/Mips/MipsSEISelLowering.cpp 3538 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
lib/Target/PowerPC/PPCISelLowering.cpp10683 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
10698 MIB = BuildMI(*thisMBB, MI, DL,
10706 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
10711 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
10713 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
10845 BuildMI(*MBB, MI, DL,
10847 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
11446 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
11447 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
11453 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
11487 BuildMI(*BB, MI, Dl, TII->get(PPC::TBEGIN)).addImm(Imm);
11508 BuildMI(*BB, MI, dl, TII->get((Mode & 1) ? PPC::MTFSB1 : PPC::MTFSB0))
11511 BuildMI(*BB, MI, dl, TII->get((Mode & 2) ? PPC::MTFSB1 : PPC::MTFSB0))
11553 BuildMI(*BB, MI, dl, TII->get(StoreOp))
11617 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF))
lib/Target/PowerPC/PPCInstrInfo.cpp 2223 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
lib/Target/RISCV/RISCVISelLowering.cpp 1200 BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
1205 BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
lib/Target/SystemZ/SystemZElimCompare.cpp 299 auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode));
lib/Target/SystemZ/SystemZISelLowering.cpp 6747 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
7368 BuildMI(*MBB, MI, DL, TII->get(Opcode))
lib/Target/SystemZ/SystemZInstrInfo.cpp 974 BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 1131 BuildMI(*MBB, *RangeBegin, RangeBegin->getDebugLoc(),
lib/Target/X86/X86FixupLEAs.cpp 598 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(LEAOpcode))
658 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(LEAOpcode))
lib/Target/X86/X86ISelLowering.cpp30188 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
30253 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
30265 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
30277 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
30439 BuildMI(*MBB, MI, DL, TII->get(XorRROpc))
30451 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrStoreOpc));
30561 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
30579 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
30877 BuildMI(*thisMBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
30925 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(Op));
31218 MachineInstr *Push = BuildMI(*BB, MI, DL, TII->get(PushF));
31241 BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI.getOperand(0).getReg());
31242 BuildMI(*BB, MI, DL, TII->get(PopF));
31260 addFrameReference(BuildMI(*BB, MI, DL,
31281 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)),
31286 addFrameReference(BuildMI(*BB, MI, DL,
31305 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
31309 addFrameReference(BuildMI(*BB, MI, DL,
lib/Target/X86/X86InstrInfo.cpp 745 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
lib/Target/X86/X86InstructionSelector.cpp 253 BuildMI(*I.getParent(), I, I.getDebugLoc(),
829 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ZextEntryIt->MovOp))
834 BuildMI(*I.getParent(), I, I.getDebugLoc(),
925 BuildMI(*I.getParent(), I, I.getDebugLoc(),
973 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1033 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1066 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1263 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY))
1411 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
1414 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
1649 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1677 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem))
1702 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1726 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TRAP));