|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 835 OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 148 MIB.addUse(Reg);
151 MIB.addUse(SrcMIB->getOperand(0).getReg());
lib/CodeGen/GlobalISel/CombinerHelper.cpp 719 MIB.addUse(MI.getOperand(0).getReg());
725 MIB.addUse(Base);
726 MIB.addUse(Offset);
lib/CodeGen/GlobalISel/IRTranslator.cpp 1129 ICall.addUse(getOrCreateVReg(**AI));
1192 .addUse(getOrCreateVReg(*CI.getOperand(0)))
1193 .addUse(getOrCreateVReg(*CI.getOperand(1)));
1366 .addUse(getOrCreateVReg(*Ptr))
1505 .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
1647 MIB.addUse(VRegs[0]);
1851 .addUse(getOrCreateVReg(*U.getOperand(0)))
1921 .addUse(getOrCreateVReg(*U.getOperand(0)))
1922 .addUse(getOrCreateVReg(*U.getOperand(1)))
2072 MIB.addUse(ValRegs[j]);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 826 .addUse(PtrReg)
931 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
1508 .addUse(DstExt)
1509 .addUse(ShiftAmtReg);
1921 .addUse(MI.getOperand(1).getReg())
1922 .addUse(MI.getOperand(2).getReg());
1952 .addUse(LHS)
1953 .addUse(RHS);
1966 .addUse(Res)
1967 .addUse(ShiftAmt);
2019 MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
2464 .addUse(PartReg));
2472 .addUse(LeftoverReg));
2483 NewInsts[InstCount++].addUse(PartRegs[J]);
2485 NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2536 .addUse(SrcRegs[I]);
2748 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2790 MIB.addUse(Unmerge.getReg(I));
3338 MIB.addUse(MI.getOperand(NumDst).getReg());
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 267 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
276 .addUse(TablePtr)
278 .addUse(IndexReg);
365 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
666 .addUse(Src)
667 .addUse(Op)
764 .addUse(Addr)
765 .addUse(CmpVal)
766 .addUse(NewVal)
789 .addUse(Addr)
790 .addUse(CmpVal)
791 .addUse(NewVal)
lib/CodeGen/GlobalISel/RegBankSelect.cpp 165 .addUse(Src);
197 MergeBuilder.addUse(SrcReg);
206 UnMergeBuilder.addUse(MO.getReg());
lib/Target/AArch64/AArch64CallLowering.cpp 171 MIB.addUse(PhysReg, RegState::Implicit);
365 MIB.addUse(AArch64::X21, RegState::Implicit);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 291 .addUse(AArch64::WZR)
292 .addUse(AArch64::WZR)
299 .addUse(StatusReg, RegState::Kill)
300 .addUse(StatusReg, RegState::Kill)
303 .addUse(StatusReg, getKillRegState(StatusDead))
375 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB);
516 .addUse(DstReg, RegState::Kill);
689 .addUse(SrcReg)
lib/Target/AArch64/AArch64FastISel.cpp 5128 .addUse(AddrReg)
5129 .addUse(DesiredReg)
5130 .addUse(NewReg);
5134 .addUse(ResultReg1)
5135 .addUse(DesiredReg)
5140 .addUse(AArch64::WZR)
5141 .addUse(AArch64::WZR)
lib/Target/AArch64/AArch64InstrInfo.cpp 1515 .addUse(Reg, RegState::Kill)
1557 .addUse(Reg, RegState::Kill)
lib/Target/AArch64/AArch64InstructionSelector.cpp 728 .addUse(SrcReg)
1001 .addUse(LHS)
1105 .addUse(ArgsAddrReg)
1106 .addUse(ListReg)
1134 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg);
1417 .addUse(CondReg)
1426 .addUse(CondReg)
1665 .addUse(I.getOperand(2).getReg())
1812 .addUse(LdReg)
2050 .addUse(SrcReg)
2106 .addUse(SrcReg)
2175 .addUse(CondReg)
2180 .addUse(TReg)
2181 .addUse(FReg)
2230 .addUse(I.getOperand(2).getReg());
2236 CmpMI = CmpMI.addUse(I.getOperand(3).getReg());
2246 .addUse(AArch64::WZR)
2247 .addUse(AArch64::WZR)
2255 .addUse(AArch64::WZR)
2256 .addUse(AArch64::WZR)
2261 .addUse(Def1Reg)
2262 .addUse(Def2Reg);
2755 .addUse(I.getOperand(1).getReg())
2763 .addUse(I.getOperand(2).getReg())
2768 .addUse(SubToRegDef)
2769 .addUse(SubToRegDef2)
3001 .addUse(ImpDefReg)
3002 .addUse(SrcReg)
3028 .addUse(InsReg)
3162 AddMI.addUse(RHS.getReg());
3188 CmpMI.addUse(RHS.getReg());
3217 TstMI.addUse(RHS);
3257 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addDef(ZReg).addUse(LHS.getReg());
3263 CmpMI.addUse(RHS.getReg());
3325 .addUse(WidenedOp2->getOperand(0).getReg())
3460 Cmp.addUse(CondDef->getOperand(3).getReg());
3730 .addUse(Src2Reg)
3761 .addUse(InsSub->getOperand(0).getReg())
3766 .addUse(EltReg);
4261 MIB.addUse(Gep->getOperand(1).getReg());
4263 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); },
4298 MIB.addUse(Gep->getOperand(1).getReg());
4301 MIB.addUse(Gep->getOperand(2).getReg());
4491 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ShiftReg); },
4629 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); },
lib/Target/AArch64/AArch64SpeculationHardening.cpp 233 .addUse(MisspeculatingTaintReg)
234 .addUse(AArch64::XZR)
371 .addUse(AArch64::SP)
377 .addUse(AArch64::XZR)
378 .addUse(AArch64::XZR)
394 .addUse(AArch64::SP)
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable)
401 .addUse(MisspeculatingTaintReg, RegState::Kill)
406 .addUse(TmpReg, RegState::Kill)
454 .addUse(Reg);
578 .addUse(SrcReg, RegState::Kill)
579 .addUse(Is64Bit ? MisspeculatingTaintReg
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 63 MIB.addUse(PhysReg, RegState::Implicit);
321 Ret.addUse(ReturnAddrVReg);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 1012 .addUse(VData);
1015 MIB.addUse(VOffset);
1017 MIB.addUse(RSrc)
1018 .addUse(SOffset)
1269 .addUse(SrcReg);
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1171 .addUse(GetReg)
1172 .addUse(ShiftAmt.getReg(0));
1305 .addUse(Src);
1382 .addUse(Const0.getReg(0))
1383 .addUse(Const1.getReg(0));
1457 .addUse(CvtHi.getReg(0))
1458 .addUse(ThirtyTwo.getReg(0));
1564 .addUse(MulVal.getReg(0))
1572 .addUse(TrigVal)
1756 .addUse(PtrReg)
1757 .addUse(PackedVal)
1903 .addUse(RHS)
1914 .addUse(FNeg.getReg(0))
1925 .addUse(RHS)
1953 .addUse(RHSExt.getReg(0))
1960 .addUse(RDst.getReg(0))
1961 .addUse(RHS)
1962 .addUse(LHS)
1994 .addUse(Mul0.getReg(0))
2122 .addUse(Use)
2142 .addUse(Reg)
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 621 .addUse(Reg);
1304 .addUse(VData);
1307 MIB.addUse(VOffset);
1309 MIB.addUse(RSrc)
1310 .addUse(SOffset)
1422 .addUse(Src0Regs[0])
1423 .addUse(Src1Regs[0]);
1427 .addUse(Src0Regs[1])
1428 .addUse(Src1Regs[1]);
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 385 B.addUse(R.first, R.second.first & ~RegState::Kill, SubReg);
lib/Target/ARM/ARMCallLowering.cpp 125 MIB.addUse(PhysReg, RegState::Implicit);
lib/Target/ARM/ARMInstructionSelector.cpp 580 .addUse(LHSReg)
581 .addUse(RHSReg)
599 .addUse(PrevRes)
777 .addUse(CondReg)
793 .addUse(TrueReg)
794 .addUse(FalseReg)
886 .addUse(AndResult)
936 .addUse(SrcReg)
1107 .addUse(OriginalValue)
lib/Target/Mips/MipsCallLowering.cpp 150 .addUse(PhysReg + (STI.isLittle() ? 0 : 1))
151 .addUse(PhysReg + (STI.isLittle() ? 1 : 0))
159 .addUse(PhysReg)
262 .addUse(ValVReg)
270 .addUse(ValVReg)
277 .addUse(ValVReg)
283 MIB.addUse(PhysReg, RegState::Implicit);
579 MIB.addUse(CalleeReg);
lib/Target/Mips/MipsInstructionSelector.cpp 278 .addUse(PseudoMULTuReg);
307 .addUse(Mips::ZERO)
320 .addUse(I.getOperand(2).getReg())
328 .addUse(I.getOperand(0).getReg())
329 .addUse(JTIndex);
337 .addUse(DestAddress)
349 .addUse(DestTmp)
350 .addUse(MF.getInfo<MipsFunctionInfo>()
358 .addUse(Dest);
440 .addUse(HILOReg);
538 .addUse(I.getOperand(1).getReg());
544 .addUse(ResultInFPR);
599 .addUse(LUiReg)
697 MIB.addUse(Instruction.RHS);
759 .addUse(Mips::ZERO)
767 .addUse(I.getOperand(2).getReg())
768 .addUse(I.getOperand(3).getReg())
775 .addUse(Mips::ZERO)
776 .addUse(Mips::FCC0)
777 .addUse(TrueInReg);
802 .addUse(LeaReg)
803 .addUse(I.getOperand(0).getReg())
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 134 .addUse(Mips::RA_64, RegState::Undef)
135 .addUse(Mips::ZERO_64);
137 MIB.addUse(Mips::AT_64, RegState::Implicit);
142 .addUse(Mips::RA, RegState::Undef)
143 .addUse(Mips::ZERO);
147 .addUse(Mips::SP)
150 MIB.addUse(Mips::AT, RegState::Implicit);
lib/Target/X86/X86CallLowering.cpp 126 MIB.addUse(PhysReg, RegState::Implicit);
441 MIB.addUse(X86::AL, RegState::Implicit);
lib/Target/X86/X86InstructionSelector.cpp 544 addFullAddress(MIB, AM).addUse(DefReg);
tools/llvm-exegesis/lib/X86/Target.cpp 656 .addUse(kLoopCounterReg)
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 703 .addUse(InitVal.getReg(0))
705 .addUse(MidVal.getReg(0))
712 .addUse(InitOtherVal.getReg(0))
714 .addUse(MidOtherVal.getReg(0))
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp 170 .addUse(Copies[0]);
176 .addUse(Copies[1]);