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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/GlobalISel/CallLowering.cpp 275 Args[i].Regs.push_back(Unmerge.getReg(PartIdx));
338 MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0));
340 MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0);
lib/CodeGen/GlobalISel/CombinerHelper.cpp 240 UndefReg = Builder.buildUndef(SrcType).getReg(0);
899 return MIB.buildConstant(Ty, SplatVal).getReg(0);
912 Val = MIB.buildMul(ExtType, ZExt, MagicMI).getReg(0);
1005 Value = MIB.buildTrunc(Ty, MemSetValue).getReg(0);
1019 Ptr = MIB.buildGEP(PtrTy, Dst, Offset).getReg(0);
1123 .getReg(0);
1124 LoadPtr = MIB.buildGEP(PtrTy, Src, Offset).getReg(0);
1130 CurrOffset == 0 ? Dst : MIB.buildGEP(PtrTy, Dst, Offset).getReg(0);
1221 LoadPtr = MIB.buildGEP(PtrTy, Src, Offset).getReg(0);
1223 LoadVals.push_back(MIB.buildLoad(CopyTy, LoadPtr, *LoadMMO).getReg(0));
1238 StorePtr = MIB.buildGEP(PtrTy, Dst, Offset).getReg(0);
lib/CodeGen/GlobalISel/IRTranslator.cpp 519 MIB.buildBrJT(Table.getReg(0), JT.JTI, JT.Reg);
542 JT.Reg = Sub.getReg(0);
555 Cst = MIB.buildZExtOrTrunc(PtrScalarTy, Cst).getReg(0);
558 auto BrCond = MIB.buildBrCond(Cmp.getReg(0), *JT.Default);
591 Cond = MIB.buildICmp(CB.PredInfo.Pred, i1Ty, CondLHS, CondRHS).getReg(0);
603 MIB.buildICmp(CmpInst::ICMP_SLE, i1Ty, CmpOpReg, CondRHS).getReg(0);
608 Cond = MIB.buildICmp(CmpInst::ICMP_ULE, i1Ty, Sub, Diff).getReg(0);
634 .getReg(0);
1084 MIRBuilder.buildGEP(PtrTy, BaseReg, OffsetMIB.getReg(0)).getReg(0);
1084 MIRBuilder.buildGEP(PtrTy, BaseReg, OffsetMIB.getReg(0)).getReg(0);
1090 IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0);
1099 MIRBuilder.buildMul(OffsetTy, ElementSizeMIB, IdxReg).getReg(0);
1103 BaseReg = MIRBuilder.buildGEP(PtrTy, BaseReg, GepOffsetReg).getReg(0);
1110 MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 640 PartRegs.push_back(K.getReg(0));
651 LeftoverRegs.push_back(K.getReg(0));
679 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
694 Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
714 MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
1138 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1143 MO.setReg(Concat.getReg(0));
1148 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1177 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1242 Unmerges.push_back(Unmerge.getReg(J));
1248 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1259 NewMergeRegs.push_back(Merge.getReg(0));
1268 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
2087 auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
2088 auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2094 MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2159 auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
2166 MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2167 MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2167 MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2790 MIB.addUse(Unmerge.getReg(I));
2816 UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
2841 ConcatOps.push_back(BuildVec.getReg(0));
3198 ResultRegs[0] = Lo.getReg(0);
3199 ResultRegs[1] = Hi.getReg(0);
3227 ResultRegs[0] = Lo.getReg(0);
3228 ResultRegs[1] = Hi.getReg(0);
3359 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3371 Factors.push_back(Mul.getReg(0));
3378 Factors.push_back(Umulh.getReg(0));
3390 FactorSum = Uaddo.getReg(0);
3391 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3391 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3395 FactorSum = Uaddo.getReg(0);
3396 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3397 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3401 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3403 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
4043 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
4046 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
4083 Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4124 Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4139 Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4152 BuildVec.push_back(Extract.getReg(0));
4211 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
4244 Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
4247 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4250 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 245 return buildGEP(Res, Op0, Cst.getReg(0));
lib/Target/AArch64/AArch64CallLowering.cpp 296 CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
325 MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef.getReg(0)})
326 .getReg(0);
330 .getReg(0);
339 .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
340 .getReg(0);
348 MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}).getReg(0);
lib/Target/AArch64/AArch64InstructionSelector.cpp 600 .addReg(Copy.getReg(0), 0, SubReg);
602 RegOp.setReg(SubRegCopy.getReg(0));
1147 Register DstReg = BuildMovK(MovZ.getReg(0),
1185 MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
1186 I.getOperand(2).setReg(Trunc.getReg(0));
2675 MIB.buildCopy(DstReg, Cmp.getReg(0));
2730 emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB);
3718 .addReg(TBL1.getReg(0), 0, AArch64::dsub);
3719 RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI);
4564 return Copy.getReg(0);
lib/Target/AArch64/AArch64LegalizerInfo.cpp 679 MI.getOperand(2).setReg(ExtCst.getReg(0));
712 MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1).getReg(), MMO);
746 auto ListTmp = MIRBuilder.buildGEP(PtrTy, List, AlignMinus1.getReg(0));
761 auto NewList = MIRBuilder.buildGEP(PtrTy, DstPtr, Size.getReg(0));
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 58 ExtReg = MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
237 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
252 B.buildInsert(BigReg, ImpDef.getReg(0), SrcReg, 0).getReg(0);
252 B.buildInsert(BigReg, ImpDef.getReg(0), SrcReg, 0).getReg(0);
537 EltMerges.push_back(Merge.getReg(0));
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1172 .addUse(ShiftAmt.getReg(0));
1255 B.buildMerge(Dst, {Src, HighAddr.getReg(0)});
1274 B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
1275 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
1297 B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
1310 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));
1382 .addUse(Const0.getReg(0))
1383 .addUse(Const1.getReg(0));
1402 Register Hi = Unmerge.getReg(1);
1419 auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)});
1419 auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)});
1450 B.buildSITOFP(S64, Unmerge.getReg(1)) :
1451 B.buildUITOFP(S64, Unmerge.getReg(1));
1453 auto CvtLo = B.buildUITOFP(S64, Unmerge.getReg(0));
1457 .addUse(CvtHi.getReg(0))
1458 .addUse(ThirtyTwo.getReg(0));
1564 .addUse(MulVal.getReg(0))
1565 .setMIFlags(Flags).getReg(0);
1567 TrigVal = B.buildFMul(Ty, SrcReg, OneOver2Pi, Flags).getReg(0);
1711 MI.getOperand(1).setReg(Cast.getReg(0));
1752 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0);
1809 AndMaskSrc = B.buildLShr(S32, LiveIn, ShiftAmt).getReg(0);
1914 .addUse(FNeg.getReg(0))
1953 .addUse(RHSExt.getReg(0))
1960 .addUse(RDst.getReg(0))
1994 .addUse(Mul0.getReg(0))
2034 B.buildGEP(DstReg, KernargPtrReg, B.buildConstant(IdxTy, Offset).getReg(0));
2067 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0));
2067 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0));
2071 return B.buildBuildVector(LLT::vector(NumElts, S32), WideRegs).getReg(0);
2089 Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 690 Register InitReg = B.buildUndef(ResTy).getReg(0);
832 Register UnmergePiece = Unmerge.getReg(PieceIdx);
856 .getReg(0);
907 Op.setReg(Merge.getReg(0));
910 Op.setReg(Merge.getReg(0));
1165 WideRegs.push_back(Unmerge.getReg(I));
1170 return B.buildMerge(LLT::vector(NumElts, S32), WideRegs).getReg(0);
1217 BaseReg = B.buildConstant(S32, Overflow).getReg(0);
1220 BaseReg = B.buildAdd(S32, BaseReg, OverflowVal).getReg(0);
1226 BaseReg = B.buildConstant(S32, 0).getReg(0);
1522 MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank);
1553 MRI.setRegBank(True.getReg(0), *DstBank);
1554 MRI.setRegBank(False.getReg(0), *DstBank);
1562 MRI.setRegBank(Sel.getReg(0), *DstBank);
1585 MRI.setRegBank(Ext.getReg(0), *SrcBank);
1586 MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank);
1587 MRI.setRegBank(Shl.getReg(0), *SrcBank);
1619 ZextLo = B.buildZExt(S32, Lo).getReg(0);
1622 Register ZextHi = B.buildZExt(S32, Hi).getReg(0);
1626 MRI.setRegBank(ShiftAmt.getReg(0), *BankHi);
1628 ShiftHi = B.buildShl(S32, ZextHi, ShiftAmt).getReg(0);
1631 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0);
1635 MRI.setRegBank(ShiftAmt.getReg(0), *BankHi);
1637 ShiftHi = B.buildShl(S32, Hi, ShiftAmt).getReg(0);
1640 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0);
1645 MRI.setRegBank(Or.getReg(0), *DstBank);
1696 MRI.setRegBank(CastSrc.getReg(0), *SrcBank);
1697 MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank);
1698 MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank);
1699 MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank);
1764 MRI.setRegBank(CastSrc.getReg(0), *SrcBank);
1765 MRI.setRegBank(InsLo.getReg(0), *DstBank);
1766 MRI.setRegBank(InsHi.getReg(0), *DstBank);
1767 MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank);
1768 MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank);
1769 MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank);
unittests/CodeGen/GlobalISel/KnownBitsTest.cpp 133 EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0)));
134 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0)));
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 691 B.buildBrCond(ICmp.getReg(0), *MidMBB);
703 .addUse(InitVal.getReg(0))
705 .addUse(MidVal.getReg(0))
712 .addUse(InitOtherVal.getReg(0))
714 .addUse(MidOtherVal.getReg(0))
718 B.buildAnd(PhiTy, Phi.getReg(0), Phi.getReg(0));
718 B.buildAnd(PhiTy, Phi.getReg(0), Phi.getReg(0));
768 B.buildInstr(TargetOpcode::G_FNEG, {LLT::scalar(64)}, {FAdd.getReg(0)},
894 Register Constant0 = B.buildConstant(S16, 1).getReg(0);
895 Register Constant1 = B.buildConstant(S16, 2).getReg(0);
949 Merge0Ops.push_back(B.buildConstant(S3, I).getReg(0));
958 Merge1Ops.push_back(B.buildConstant(S3, I).getReg(0));
964 Merge2Ops.push_back(B.buildConstant(S8, I).getReg(0));
1040 auto Merge = B.buildMerge(P0, {Lo.getReg(0), Hi.getReg(0)});
1040 auto Merge = B.buildMerge(P0, {Lo.getReg(0), Hi.getReg(0)});
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 322 bool match = mi_match(MIBAdd.getReg(0), *MRI, m_GAdd(m_Reg(), m_Reg()));
324 match = mi_match(MIBAdd.getReg(0), *MRI, m_OneUse(m_GAdd(m_Reg(), m_Reg())));