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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 752 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 151 MIB.addUse(SrcMIB->getOperand(0).getReg());
167 return MRI.getType(SrcMIB->getOperand(0).getReg());
180 return SrcMIB->getOperand(0).getReg();
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 107 assert(canPerformCSEForOpc(MIB->getOpcode()) &&
132 return buildCopy(Op.getReg(), MIB->getOperand(0).getReg());
lib/CodeGen/GlobalISel/CallLowering.cpp 261 assert(Unmerge->getNumOperands() == NumParts + 1);
468 return MIB->getOperand(0).getReg();
lib/CodeGen/GlobalISel/IRTranslator.cpp 1624 MIB->copyIRFlags(CI);
1911 Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 618 MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
1002 MO1.setReg(TruncMIB->getOperand(0).getReg());
1038 ->getOperand(0)
1057 ->getOperand(0)
1066 ->getOperand(0)
1085 MO.setReg(ExtB->getOperand(0).getReg());
1093 MO.setReg(ExtB->getOperand(0).getReg());
1241 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1306 MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
2003 Register ZeroReg = Zero->getOperand(0).getReg();
2269 MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2270 MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2782 const int NumUnmerge = Unmerge->getNumOperands() - 1;
3611 DstRegs.push_back(Inst->getOperand(0).getReg());
3618 DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3658 DstRegs.push_back(Select->getOperand(0).getReg());
3664 DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3727 Op = MIBOp->getOperand(0).getReg();
3781 MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 1179 MIB->setFlags(*Flags);
lib/CodeGen/MachineSSAUpdater.cpp 198 if (unsigned ConstVal = InsertedPHI->isConstantValuePHI()) {
199 InsertedPHI->eraseFromParent();
207 return InsertedPHI->getOperand(0).getReg();
lib/CodeGen/SelectionDAG/FastISel.cpp 1028 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 303 const MCInstrDesc &MCID = MIB->getDesc();
345 unsigned Idx = MIB->getNumOperands();
347 MIB->getOperand(Idx-1).isReg() &&
348 MIB->getOperand(Idx-1).isImplicit())
970 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
1081 GroupIdx.push_back(MIB->getNumOperands());
1124 MIB->tieOperands(DefIdx + j, UseIdx + j);
1137 if (MIB->readsRegister(Reg, TRI)) {
1139 MIB->findRegisterDefOperand(Reg, false, false, TRI);
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1708 assert(PHI->isPHI() &&
1710 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1834 MachineBasicBlock *PHIBB = PHI->getParent();
1835 assert(PHI->isPHI() &&
1887 MachineBasicBlock *PHIBB = PHI->getParent();
1888 assert(PHI->isPHI() &&
lib/CodeGen/TargetLoweringBase.cpp 1075 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1087 MIB->addMemOperand(MF, MMO);
1092 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
lib/Target/AArch64/AArch64CallLowering.cpp 181 ->getOperand(0)
880 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) {
896 MIB->getOperand(1).setImm(FPDiff);
911 MIB->getOperand(0).setReg(constrainOperandRegClass(
913 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
997 MIB->getOperand(0).setReg(constrainOperandRegClass(
999 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
lib/Target/AArch64/AArch64FastISel.cpp 1138 const MCInstrDesc &II = MIB->getDesc();
lib/Target/AArch64/AArch64InstructionSelector.cpp 1123 MovZ->addOperand(MF, I.getOperand(1));
1124 MovZ->getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_G0 |
1126 MovZ->addOperand(MF, MachineOperand::CreateImm(0));
1136 MovI->addOperand(MF, MachineOperand::CreateGA(
1137 GV, MovZ->getOperand(1).getOffset(), Flags));
1139 MovI->addOperand(
1141 MovZ->getOperand(1).getOffset(), Flags));
1143 MovI->addOperand(MF, MachineOperand::CreateImm(Offset));
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 901 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
919 MIBKill->getOperand(2).setImplicit();
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 2066 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 830 unsigned NumPieces = Unmerge->getNumOperands() - 1;
1164 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
lib/Target/AMDGPU/GCNDPPCombine.cpp 212 DPPInst->getOperand(NumOperands).setIsKill(false);
lib/Target/AMDGPU/R600ISelLowering.cpp 364 MIB->getOperand(Idx) = MI.getOperand(1);
lib/Target/AMDGPU/SIInstrInfo.cpp 2231 I = MIB->getIterator();
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1137 SDWAInst->tieOperands(PreserveDstIdx, SDWAInst->getNumOperands() - 1);
1137 SDWAInst->tieOperands(PreserveDstIdx, SDWAInst->getNumOperands() - 1);
1160 SDWAInst->eraseFromParent();
lib/Target/AMDGPU/SIRegisterInfo.cpp 1130 const bool IsVOP2 = MIB->getOpcode() == AMDGPU::V_ADD_U32_e32;
lib/Target/ARM/ARMBaseInstrInfo.cpp 991 Mov->addRegisterDefined(DestReg, TRI);
993 Mov->addRegisterKilled(SrcReg, TRI);
2273 if (NewMI->hasOptionalDef())
2282 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
2282 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
2293 NewMI->clearKillInfo();
lib/Target/ARM/ARMCallLowering.cpp 534 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
536 *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
lib/Target/ARM/ARMExpandPseudoInsts.cpp 643 MIB->addRegisterKilled(SrcReg, TRI, true);
914 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
1642 MIB->addRegisterKilled(SrcReg, TRI, true);
lib/Target/ARM/ARMISelLowering.cpp10219 MIB->getOperand(5).setReg(ARM::CPSR);
10220 MIB->getOperand(5).setIsDef(true);
lib/Target/ARM/ARMInstructionSelector.cpp 239 Register VReg0 = MIB->getOperand(0).getReg();
244 Register VReg1 = MIB->getOperand(1).getReg();
249 Register VReg2 = MIB->getOperand(2).getReg();
255 MIB->setDesc(TII.get(ARM::VMOVDRR));
271 Register VReg0 = MIB->getOperand(0).getReg();
276 Register VReg1 = MIB->getOperand(1).getReg();
281 Register VReg2 = MIB->getOperand(2).getReg();
287 MIB->setDesc(TII.get(ARM::VMOVRRD));
483 : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
483 : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
484 DbgLoc(MIB->getDebugLoc()) {}
530 auto ResReg = MIB->getOperand(0).getReg();
535 static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
538 MIB->eraseFromParent();
542 auto LHSReg = MIB->getOperand(2).getReg();
543 auto RHSReg = MIB->getOperand(3).getReg();
568 MIB->eraseFromParent();
615 auto GV = MIB->getOperand(1).getGlobal();
621 auto &MBB = *MIB->getParent();
632 assert((MIB->getOpcode() == ARM::LDRi12 ||
633 MIB->getOpcode() == ARM::t2LDRpci) &&
647 if (MIB->getOpcode() == ARM::LDRi12)
676 MIB->setDesc(TII.get(Opc));
683 MIB->getOperand(1).setTargetFlags(TargetFlags);
687 auto ResultReg = MIB->getOperand(0).getReg();
690 MIB->getOperand(0).setReg(AddressReg);
692 auto InsertBefore = std::next(MIB->getIterator());
693 auto MIBLoad = BuildMI(MBB, InsertBefore, MIB->getDebugLoc(),
714 MIB->setDesc(TII.get(Opc));
721 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
726 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
734 MIB->setDesc(TII.get(Opcodes.ADDrr));
735 MIB->RemoveOperand(1);
746 MIB->setDesc(TII.get(Opcodes.MOVi32imm));
749 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad));
750 MIB->RemoveOperand(1);
755 MIB->setDesc(TII.get(Opcodes.MOVi32imm));
757 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs));
768 auto &MBB = *MIB->getParent();
769 auto InsertBefore = std::next(MIB->getIterator());
770 auto &DbgLoc = MIB->getDebugLoc();
773 auto CondReg = MIB->getOperand(1).getReg();
785 auto ResReg = MIB->getOperand(0).getReg();
786 auto TrueReg = MIB->getOperand(2).getReg();
787 auto FalseReg = MIB->getOperand(3).getReg();
799 MIB->eraseFromParent();
806 MIB->setDesc(TII.get(ARM::MOVsr));
941 MIB->eraseFromParent();
997 MIB->setDesc(TII.get(LoadOpcode));
998 MIB->RemoveOperand(1);
lib/Target/ARM/ARMLowOverheadLoops.cpp 405 MIB->getOperand(5).setIsDef(true);
lib/Target/ARM/Thumb1InstrInfo.cpp 63 ->addRegisterDead(ARM::CPSR, RegInfo);
lib/Target/ARM/Thumb2SizeReduction.cpp 922 MIB->getOperand(0).setIsKill(false);
923 MIB->getOperand(0).setIsDef(true);
924 MIB->getOperand(0).setIsDead(true);
lib/Target/AVR/AVRExpandPseudoInsts.cpp 163 MIBHI->getOperand(3).setIsDead();
166 MIBHI->getOperand(4).setIsKill();
191 MIBLO->getOperand(3).setIsDead();
199 MIBHI->getOperand(3).setIsDead();
239 MIBLO->getOperand(3).setIsDead();
249 MIBHI->getOperand(3).setIsDead();
309 MIBHI->getOperand(3).setIsDead();
312 MIBHI->getOperand(4).setIsKill();
344 MIBLO->getOperand(4).setIsKill();
352 MIBHI->getOperand(3).setIsDead();
355 MIBHI->getOperand(4).setIsKill();
403 MIBLO->getOperand(2).setIsDead();
410 MIBHI->getOperand(2).setIsDead();
440 MIBHI->getOperand(2).setIsDead();
443 MIBHI->getOperand(3).setIsKill();
468 MIBLO->getOperand(3).setIsKill();
475 MIBHI->getOperand(2).setIsDead();
478 MIBHI->getOperand(3).setIsKill();
1269 MIBHI->getOperand(3).setIsDead();
1272 MIBHI->getOperand(4).setIsKill();
1300 MIBLO->getOperand(2).setIsDead();
1303 MIBLO->getOperand(3).setIsKill();
1343 MIBLO->getOperand(2).setIsDead();
1346 MIBLO->getOperand(3).setIsKill();
1381 MOV->getOperand(1).setIsKill();
1402 SBC->getOperand(3).setIsDead();
1405 SBC->getOperand(4).setIsKill();
1441 EOR->getOperand(3).setIsDead();
lib/Target/Hexagon/HexagonConstPropagation.cpp 3159 for (auto &Op : NI->operands())
3161 NI->eraseFromParent();
lib/Target/Hexagon/HexagonGenMux.cpp 341 NewMux->clearKillInfo();
lib/Target/Hexagon/HexagonInstrInfo.cpp 1600 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1601 MI.addOperand(T->getOperand(i));
1603 MachineBasicBlock::instr_iterator TI = T->getIterator();
lib/Target/Lanai/LanaiInstrInfo.cpp 534 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
534 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
545 NewMI->clearKillInfo();
lib/Target/Mips/MipsCallLowering.cpp 638 if (MIB->getOpcode() == Mips::JALRPseudo) {
lib/Target/Mips/MipsISelLowering.cpp 1282 MIB->getOperand(0).setSubReg(Mips::sub_32);
lib/Target/Mips/MipsInstrInfo.cpp 648 MIB->RemoveOperand(0);
lib/Target/SystemZ/SystemZInstrInfo.cpp 828 MIB->addRegisterKilled(SrcReg, TRI);
lib/Target/X86/X86CallLowering.cpp 142 ExtReg = MIB->getOperand(0).getReg();
451 MIB->getOperand(0).setReg(constrainOperandRegClass(
453 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
lib/Target/X86/X86CmovConversion.cpp 841 LLVM_DEBUG(dbgs() << "\tTo: "; MIB->dump());
lib/Target/X86/X86FastISel.cpp 229 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg,
230 MIB->getNumOperands() +
474 MIB->addMemOperand(*FuncInfo.MF, MMO);
651 MIB->addMemOperand(*FuncInfo.MF, MMO);
688 MIB->addMemOperand(*FuncInfo.MF, MMO);
3802 MIB->addMemOperand(*FuncInfo.MF, MMO);
lib/Target/X86/X86FlagsCopyLowering.cpp 747 LLVM_DEBUG(dbgs() << " save cond: "; SetI->dump());
772 LLVM_DEBUG(dbgs() << " test cond: "; TestI->dump());
824 LLVM_DEBUG(dbgs() << " add cond: "; AddI->dump());
lib/Target/X86/X86FrameLowering.cpp 389 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
2983 ->getOperand(3)
lib/Target/X86/X86InstrInfo.cpp 2462 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2464 MIB->addOperand(BranchCond[0]); // Condition.
3880 Register Reg = MIB->getOperand(0).getReg();
3881 MIB->setDesc(Desc);
3887 assert(MIB->getOperand(1).getReg() == Reg &&
3888 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3901 MIB->setDesc(Desc);
3908 MachineBasicBlock &MBB = *MIB->getParent();
3909 DebugLoc DL = MIB->getDebugLoc();
3910 Register Reg = MIB->getOperand(0).getReg();
3918 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3927 MachineBasicBlock &MBB = *MIB->getParent();
3928 DebugLoc DL = MIB->getDebugLoc();
3929 int64_t Imm = MIB->getOperand(1).getImm();
3936 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3937 MIB->getOpcode() == X86::MOV32ImmSExti8);
3943 MIB->setDesc(TII.get(MIB->getOpcode() ==
3943 MIB->setDesc(TII.get(MIB->getOpcode() ==
3952 MIB->setDesc(TII.get(X86::POP64r));
3953 MIB->getOperand(0)
3954 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3956 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
3959 MIB->setDesc(TII.get(X86::POP32r));
3984 MachineBasicBlock &MBB = *MIB->getParent();
3985 DebugLoc DL = MIB->getDebugLoc();
3986 Register Reg = MIB->getOperand(0).getReg();
3988 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3999 MIB->setDebugLoc(DL);
4000 MIB->setDesc(TII.get(X86::MOV64rm));
4005 MachineBasicBlock &MBB = *MIB->getParent();
4010 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4011 MIB->setDesc(TII.get(XorOp));
4024 Register DestReg = MIB->getOperand(0).getReg();
4028 MIB->setDesc(LoadDesc);
4031 MIB->setDesc(BroadcastDesc);
4034 MIB->getOperand(0).setReg(DestReg);
4047 Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4051 MIB->setDesc(StoreDesc);
4054 MIB->setDesc(ExtractDesc);
4057 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4065 MIB->setDesc(Desc);
4066 int64_t ShiftAmt = MIB->getOperand(2).getImm();
4068 MIB->RemoveOperand(2);
4070 MIB.addReg(MIB->getOperand(1).getReg(),
4071 getUndefRegState(MIB->getOperand(1).isUndef()));
4108 Register SrcReg = MIB->getOperand(0).getReg();
4110 MIB->getOperand(0).setReg(XReg);
4120 Register SrcReg = MIB->getOperand(0).getReg();
4128 MIB->getOperand(0).setReg(SrcReg);
4134 Register SrcReg = MIB->getOperand(0).getReg();
4138 MIB->getOperand(0).setReg(XReg);
4148 MIB->getOperand(0).setReg(ZReg);
4157 Register Reg = MIB->getOperand(0).getReg();
4159 MIB->setDesc(get(X86::VCMPPSYrri));
4164 Register Reg = MIB->getOperand(0).getReg();
4165 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4174 Register Reg = MIB->getOperand(0).getReg();
4175 Register MaskReg = MIB->getOperand(1).getReg();
4176 unsigned MaskState = getRegState(MIB->getOperand(1));
4180 MIB->setDesc(get(Opc));
4212 Register Reg = MIB->getOperand(0).getReg();
4215 MIB->getOperand(0).setReg(Reg32);
4243 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4244 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4245 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4246 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4247 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4248 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4249 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4250 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4251 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4252 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4253 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
lib/Target/X86/X86SpeculativeLoadHardening.cpp 485 ZeroI->findRegisterDefOperand(X86::EFLAGS);
764 CMovI->findRegisterUseOperand(X86::EFLAGS)->setIsKill(true);
767 LLVM_DEBUG(dbgs() << " Inserting cmov: "; CMovI->dump();
1114 LLVM_DEBUG(dbgs() << " Inserting mov: "; AddrI->dump();
1126 LLVM_DEBUG(dbgs() << " Inserting lea: "; AddrI->dump();
1153 LLVM_DEBUG(dbgs() << " Inserting cmp: "; CheckI->dump(); dbgs() << "\n");
1166 LLVM_DEBUG(dbgs() << " Inserting lea: "; AddrI->dump(); dbgs() << "\n");
1172 LLVM_DEBUG(dbgs() << " Inserting cmp: "; CheckI->dump(); dbgs() << "\n");
1184 CMovI->findRegisterUseOperand(X86::EFLAGS)->setIsKill(true);
1186 LLVM_DEBUG(dbgs() << " Inserting cmov: "; CMovI->dump(); dbgs() << "\n");
1915 ShiftI->addRegisterDead(X86::EFLAGS, TRI);
1920 OrI->addRegisterDead(X86::EFLAGS, TRI);
1940 ShiftI->addRegisterDead(X86::EFLAGS, TRI);
2054 LLVM_DEBUG(dbgs() << " Inserting mov: "; MovI->dump(); dbgs() << "\n");
2065 LLVM_DEBUG(dbgs() << " Inserting broadcast: "; BroadcastI->dump();
2076 LLVM_DEBUG(dbgs() << " Inserting or: "; OrI->dump(); dbgs() << "\n");
2096 LLVM_DEBUG(dbgs() << " Inserting broadcast: "; BroadcastI->dump();
2107 LLVM_DEBUG(dbgs() << " Inserting or: "; OrI->dump(); dbgs() << "\n");
2118 OrI->addRegisterDead(X86::EFLAGS, TRI);
2120 LLVM_DEBUG(dbgs() << " Inserting or: "; OrI->dump(); dbgs() << "\n");
2130 LLVM_DEBUG(dbgs() << " Inserting shrx: "; ShiftI->dump();
2311 OrI->addRegisterDead(X86::EFLAGS, TRI);
2313 LLVM_DEBUG(dbgs() << " Inserting or: "; OrI->dump(); dbgs() << "\n");
2565 CMovI->findRegisterUseOperand(X86::EFLAGS)->setIsKill(true);
2567 LLVM_DEBUG(dbgs() << " Inserting cmov: "; CMovI->dump(); dbgs() << "\n");
lib/Target/XCore/XCoreFrameLowering.cpp 266 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
404 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
unittests/CodeGen/GlobalISel/CSETest.cpp 34 EXPECT_EQ(MIBAddCopy->getOpcode(), TargetOpcode::COPY);
62 EXPECT_EQ(TargetOpcode::G_BUILD_VECTOR, Splat0->getOpcode());
63 EXPECT_EQ(Splat0->getOperand(1).getReg(), Splat0->getOperand(2).getReg());
63 EXPECT_EQ(Splat0->getOperand(1).getReg(), Splat0->getOperand(2).getReg());
64 EXPECT_EQ(&*MIBCst, MRI->getVRegDef(Splat0->getOperand(1).getReg()));
67 EXPECT_EQ(TargetOpcode::G_BUILD_VECTOR, FSplat->getOpcode());
68 EXPECT_EQ(FSplat->getOperand(1).getReg(), FSplat->getOperand(2).getReg());
68 EXPECT_EQ(FSplat->getOperand(1).getReg(), FSplat->getOperand(2).getReg());
69 EXPECT_EQ(&*MIBFP0, MRI->getVRegDef(FSplat->getOperand(1).getReg()));
95 EXPECT_TRUE(MIBAdd1->getOpcode() != TargetOpcode::COPY);
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp 31 bool match = mi_match(MIBCAdd->getOperand(0).getReg(), *MRI, m_ICst(Cst));
38 match = mi_match(MIBCAdd1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
50 match = mi_match(MIBCSub->getOperand(0).getReg(), *MRI, m_ICst(Cst));
58 match = mi_match(MIBCSext1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
66 match = mi_match(MIBCSext2->getOperand(0).getReg(), *MRI, m_ICst(Cst));
84 ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
85 MIBCst2->getOperand(0).getReg(), *MRI);
89 ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
90 MIBFCst2->getOperand(0).getReg(), *MRI);
96 ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst1->getOperand(0).getReg(),
97 MIBCst2->getOperand(0).getReg(), *MRI);
101 ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst2->getOperand(0).getReg(),
102 MIBFCst1->getOperand(0).getReg(), *MRI);
108 ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBCst1->getOperand(0).getReg(),
109 MIBCst2->getOperand(0).getReg(), *MRI);
113 ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBFCst2->getOperand(0).getReg(),
114 MIBCst2->getOperand(0).getReg(), *MRI);
120 ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBCst1->getOperand(0).getReg(),
121 MIBCst2->getOperand(0).getReg(), *MRI);
125 ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBFCst1->getOperand(0).getReg(),
126 MIBCst2->getOperand(0).getReg(), *MRI);
132 ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
133 MIBCst2->getOperand(0).getReg(), *MRI);
137 ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
138 MIBFCst2->getOperand(0).getReg(), *MRI);
144 ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
145 MIBCst2->getOperand(0).getReg(), *MRI);
149 ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
150 MIBFCst2->getOperand(0).getReg(), *MRI);
156 ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
157 MIBCst2->getOperand(0).getReg(), *MRI);
161 ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
162 MIBFCst2->getOperand(0).getReg(), *MRI);
168 ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
169 MIBCst2->getOperand(0).getReg(), *MRI);
173 ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
174 MIBFCst2->getOperand(0).getReg(), *MRI);
180 ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
181 MIBCst2->getOperand(0).getReg(), *MRI);
185 ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
186 MIBFCst2->getOperand(0).getReg(), *MRI);
192 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
193 MIBCst2->getOperand(0).getReg(), *MRI);
197 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
198 MIBFCst2->getOperand(0).getReg(), *MRI);
204 ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
205 MIBCst2->getOperand(0).getReg(), *MRI);
209 ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
210 MIBFCst2->getOperand(0).getReg(), *MRI);
216 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
217 MIBCst2->getOperand(0).getReg(), *MRI);
221 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
222 MIBFCst2->getOperand(0).getReg(), *MRI);
228 ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
229 MIBCst2->getOperand(0).getReg(), *MRI);
233 ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
234 MIBFCst2->getOperand(0).getReg(), *MRI);
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp 89 B.buildAdd(MIBAdd->getOperand(0), MIBAdd->getOperand(1), MIBAdd->getOperand(2));
89 B.buildAdd(MIBAdd->getOperand(0), MIBAdd->getOperand(1), MIBAdd->getOperand(2));
89 B.buildAdd(MIBAdd->getOperand(0), MIBAdd->getOperand(1), MIBAdd->getOperand(2));
333 Register RegC0 = B.buildConstant(S32, 0)->getOperand(0).getReg();
334 Register RegC1 = B.buildConstant(S32, 1)->getOperand(0).getReg();
335 Register RegC2 = B.buildConstant(S32, 2)->getOperand(0).getReg();
336 Register RegC3 = B.buildConstant(S32, 3)->getOperand(0).getReg();
344 B.buildMerge(V2x32, {RegC0, RegC1})->getOperand(0).getReg();
346 B.buildMerge(V2x32, {RegC2, RegC3})->getOperand(0).getReg();
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 39 bool match = mi_match(MIBCst->getOperand(0).getReg(), *MRI, m_ICst(Cst));
52 mi_match(MIBAdd->getOperand(0).getReg(), *MRI, m_GAdd(m_Reg(), m_Reg()));
55 match = mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
65 match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
68 EXPECT_EQ(Src0, MIBAdd->getOperand(0).getReg());
72 match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
84 match = mi_match(MIBMul2->getOperand(0).getReg(), *MRI,
92 match = mi_match(MIBSub->getOperand(0).getReg(), *MRI,
99 match = mi_match(MIBFMul->getOperand(0).getReg(), *MRI,
108 match = mi_match(MIBFSub->getOperand(0).getReg(), *MRI,
116 match = mi_match(MIBAnd->getOperand(0).getReg(), *MRI,
125 match = mi_match(MIBOr->getOperand(0).getReg(), *MRI,
144 mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg()));
149 match = mi_match(MIBFNeg->getOperand(0).getReg(), *MRI, m_GFNeg(m_Reg(Src)));
151 EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
153 match = mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg(Src)));
155 EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
160 match = mi_match(MIBFCst->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP));
171 match = mi_match(MIBFCst64->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP64));
183 match = mi_match(MIBFCst16->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP16));
208 mi_match(MIBTrunc->getOperand(0).getReg(), *MRI, m_GTrunc(m_Reg(Src0)));
212 mi_match(MIBAExt->getOperand(0).getReg(), *MRI, m_GAnyExt(m_Reg(Src0)));
214 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
216 match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI, m_GSExt(m_Reg(Src0)));
218 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
220 match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI, m_GZExt(m_Reg(Src0)));
222 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
225 match = mi_match(MIBAExt->getOperand(0).getReg(), *MRI,
230 match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI,
235 match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI,
250 EXPECT_FALSE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
252 EXPECT_TRUE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
259 mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_GBitcast(m_Reg())));
261 mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_SpecificType(v2s32)));
263 mi_match(MIBCast->getOperand(1).getReg(), *MRI, m_SpecificType(s64)));
272 bool match = mi_match(MIBPtrToInt->getOperand(0).getReg(), *MRI,
288 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
295 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
299 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
307 MIBAdd->getOperand(0).getReg(), *MRI,