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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 453 for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
include/llvm/CodeGen/MachineRegisterInfo.h 1163 MachineInstr *operator->() const { return &operator*(); }
lib/CodeGen/CalcSpillWeights.cpp 209 MachineInstr *mi = &*(I++);
lib/CodeGen/DeadMachineInstructionElim.cpp 84 for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
lib/CodeGen/GlobalISel/CombinerHelper.cpp 402 for (auto &UseMI : MRI.use_instructions(LoadValue.getReg())) {
573 for (auto &Use : MRI.use_instructions(Base)) {
600 for (auto &GEPUse : MRI.use_instructions(Use.getOperand(0).getReg())) {
673 for (auto &UseMI : MRI.use_instructions(Addr)) {
lib/CodeGen/GlobalISel/GISelChangeObserver.cpp 20 for (auto &ChangingMI : MRI.use_instructions(Reg)) {
lib/CodeGen/GlobalISel/InstructionSelect.cpp 194 MI = &*MRI.def_instr_begin(VReg);
196 MI = &*MRI.use_instr_begin(VReg);
lib/CodeGen/GlobalISel/Localizer.cpp 184 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
lib/CodeGen/InlineSpiller.cpp 293 MachineInstr &MI = *RI++;
332 MachineInstr &MI = *RI++;
450 MachineInstr &MI = *UI++;
650 MachineInstr &MI = *RegI++;
970 MachineInstr *MI = &*(RegI++);
1096 MachineInstr &MI = *(RI++);
lib/CodeGen/LiveIntervals.cpp 462 for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
lib/CodeGen/LiveRangeShrink.cpp 198 MachineInstr &DefInstr = *MRI.def_instr_begin(Reg);
lib/CodeGen/MachineCSE.cpp 441 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
444 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
473 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
487 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(CSReg)) {
lib/CodeGen/MachineLICM.cpp 775 for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) {
969 for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) {
1066 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
1097 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
lib/CodeGen/MachinePipeliner.cpp 779 MachineInstr *UseMI = &*UI;
lib/CodeGen/MachineRegisterInfo.cpp 405 return !I.atEnd() ? &*I : nullptr;
416 return &*I;
508 for (MachineInstr &I : use_instructions(Reg))
551 MachineInstr *UseMI = &*I;
lib/CodeGen/MachineSink.cpp 559 for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) {
996 for (auto &User : MRI.use_instructions(MO.getReg())) {
lib/CodeGen/ModuloSchedule.cpp 1340 for (MachineInstr &MI : MRI.use_instructions(Def.getReg())) {
1683 for (MachineInstr &Use : MRI.use_instructions(OldR))
1744 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) {
lib/CodeGen/OptimizePHIs.cpp 156 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) {
lib/CodeGen/PHIElimination.cpp 223 for (MachineInstr &DI : MRI.def_instructions(VirtReg))
lib/CodeGen/PHIEliminationUtils.cpp 36 for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
lib/CodeGen/PeepholeOptimizer.cpp 489 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
566 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
1512 MachineInstr &MI = *(MRI->use_instr_nodbg_begin(Reg));
1867 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {
lib/CodeGen/RegAllocBase.cpp 122 MI = &*(I++);
lib/CodeGen/RegAllocFast.cpp 283 for (const MachineInstr &UseInst : MRI->reg_nodbg_instructions(VirtReg)) {
302 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
646 for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) {
787 const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
lib/CodeGen/RegAllocGreedy.cpp 2873 for (const MachineInstr &Instr : MRI->reg_nodbg_instructions(Reg)) {
lib/CodeGen/RegisterCoalescer.cpp 1674 MachineInstr *UseMI = &*(I++);
2053 CopyMI = &*MRI->use_instr_nodbg_begin(SrcReg);
3515 for (const MachineInstr &MI : MRI->reg_nodbg_instructions(DstReg))
3540 for (const MachineInstr &MI : MRI->reg_nodbg_instructions(SrcReg)) {
lib/CodeGen/SelectionDAG/FastISel.cpp 280 for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) {
308 for (MachineInstr &DbgVal : MRI.use_instructions(DefReg)) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 615 MachineInstr *UseMI = &*(UI++);
lib/CodeGen/TailDuplicator.cpp 290 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
lib/CodeGen/TwoAddressInstructionPass.cpp 346 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
527 MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
1026 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 212 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
246 if (getSrcFromCopy(&*Use, MRI, SubReg) || isTransformable(*Use))
246 if (getSrcFromCopy(&*Use, MRI, SubReg) || isTransformable(*Use))
305 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
324 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 681 for (const MachineInstr &UseMI :
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 150 MachineInstr *UseI = &*(UI++);
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1771 MachineInstr &UseMI = *MRI.use_instr_nodbg_begin(CondDef);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 1029 for (MachineInstr &Other : MRI.def_instructions(Reg)) {
lib/Target/AMDGPU/GCNRegBankReassign.cpp 575 for (auto &MI : MRI->use_nodbg_instructions(SrcReg)) {
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 237 LLVM_DEBUG(dbgs() << " "; (*It).dump(); dbgs() << " ->");
238 SwizzleInput(*It, RemapChan);
239 LLVM_DEBUG((*It).dump());
285 if (!canSwizzle(*It))
357 RemoveMI(&(*It));
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 252 MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
436 for (auto &MI : MRI.def_instructions(Reg)) {
lib/Target/AMDGPU/SIInstrInfo.cpp 6495 for (auto &UseInst : MRI.use_nodbg_instructions(VReg)) {
lib/Target/AMDGPU/SILowerI1Copies.cpp 601 for (MachineInstr &Use : MRI->use_instructions(DstReg))
714 for (MachineInstr &Use : MRI->use_instructions(DstReg))
lib/Target/AMDGPU/SIMachineScheduler.cpp 315 const MachineInstr* MI = &*UI;
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 418 for (auto& U : MRI.use_nodbg_instructions(SavedExec)) {
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 454 for (MachineInstr &UseInst : MRI->use_nodbg_instructions(PotentialMO->getReg())) {
lib/Target/AMDGPU/SIWholeQuadMode.cpp 303 for (MachineInstr &DefMI : MRI->def_instructions(Use.getReg()))
366 for (MachineInstr &DefMI : MRI->def_instructions(Reg))
lib/Target/ARC/ARCOptAddrMode.cpp 219 for (auto &Add : MRI->use_nodbg_instructions(B)) {
304 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) {
lib/Target/ARM/A15SDOptimizer.cpp 221 for (MachineInstr &Use : MRI->use_instructions(Reg)) {
lib/Target/ARM/ARMBaseInstrInfo.cpp 2919 MachineInstr *PotentialAND = &*UI;
lib/Target/ARM/MLxExpansionPass.cpp 122 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg);
130 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
lib/Target/Hexagon/BitTracker.cpp 985 for (MachineInstr &UseI : MRI.use_nodbg_instructions(Reg))
lib/Target/Hexagon/HexagonConstPropagation.cpp 786 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1456 MachineInstr *MI = &*I;
lib/Target/Mips/MipsRegisterBankInfo.cpp 175 for (MachineInstr &UseMI : MRI.use_instructions(Reg)) {
203 Ret = &(*MRI.use_instr_begin(Ret->getOperand(0).getReg()));
lib/Target/PowerPC/PPCBranchCoalescing.cpp 429 for (auto &Use : MRI->use_instructions(Def.getReg())) {
540 for (auto &Use : MRI->use_instructions(Def.getReg())) {
lib/Target/PowerPC/PPCInstrInfo.cpp 1701 MachineInstr *UseMI = &*I;
1727 if (&*J == &*I) {
1764 MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1877 MachineInstr *UseMI = &*I;
2828 for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
lib/Target/PowerPC/PPCMIPeephole.cpp 537 MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines));
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 497 for (MachineInstr &UseMI :
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 676 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
719 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
761 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
lib/Target/SystemZ/SystemZRegisterInfo.cpp 99 for (auto &Use : MRI->reg_instructions(Reg)) {
132 for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
151 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp 66 for (const auto &Def : MRI.def_instructions(Reg))
lib/Target/X86/X86DomainReassignment.cpp 583 for (auto &UseMI : MRI->use_nodbg_instructions(CurReg)) {
lib/Target/X86/X86FixupSetCC.cpp 111 for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
lib/Target/X86/X86InstrInfo.cpp 473 MachineInstr *DefMI = &*I;
lib/Target/X86/X86SpeculativeLoadHardening.cpp 2162 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) {
usr/include/c++/7.4.0/bits/predefined_ops.h 283 { return bool(_M_pred(*__it)); }
351 { return !bool(_M_pred(*__it)); }