reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/MachinePipeliner.cpp

  696           if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, TRI) &&
  697               TII->getMemOperandWithOffset(MI, BaseOp2, Offset2, TRI)) {
  700               assert(TII->areMemAccessesTriviallyDisjoint(LdMI, MI) &&
 1039     if (TII->isZeroCost(MI->getOpcode()))
 2060   if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI))
 2079   if (!TII->getIncrementValue(*BaseDef, D) && D >= 0)
 2099   if (TII->isPostIncrement(*MI))
 2102   if (!TII->getBaseAndOffsetPosition(*MI, BasePosLd, OffsetPosLd))
 2121   if (!TII->isPostIncrement(*PrevDef))
 2125   if (!TII->getBaseAndOffsetPosition(*PrevDef, BasePos1, OffsetPos1))
 2134   bool Disjoint = TII->areMemAccessesTriviallyDisjoint(*NewMI, *PrevDef);
 2157     if (!TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
 2239   if (!TII->getMemOperandWithOffset(*SI, BaseOpS, OffsetS, TRI) ||
 2240       !TII->getMemOperandWithOffset(*DI, BaseOpD, OffsetD, TRI))
 2256   if (!LoopDef || !TII->getIncrementValue(*LoopDef, D))
 2777           if (TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos)) {

lib/CodeGen/MachineScheduler.cpp

 3308   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));

lib/CodeGen/MacroFusion.cpp

   71       dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - "
   72              << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';);
  147   const TargetInstrInfo &TII = *DAG.TII;

lib/CodeGen/PostRASchedulerList.cpp

  684       TII->insertNoop(*BB, RegionEnd);

lib/CodeGen/ScheduleDAG.cpp

   72   return &TII->get(Node->getMachineOpcode());

lib/CodeGen/ScoreboardHazardRecognizer.cpp

  179   if (DAG->TII->isZeroCost(MCID->Opcode))

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

  235     if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
  254     const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
  511     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
  572         MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

  581           Node->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
  584         SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
  787           SUNode->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
  858         SUNode->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
  875           SUNode->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
  984   if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
 1034     const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
 1143       !TII->canCopyGluedNodeDuringSchedule(N)) {
 1163     if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) {
 1395     if (Node->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
 1402         if (!IsChainDependent(Gen, Node, 0, TII) &&
 1412     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
 1556     MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

  212     const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
  241     if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
  274     if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
  315     const MCInstrDesc &MCID = TII->get(Opc);
  373       if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
  391           if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
  449       const MCInstrDesc &MCID = TII->get(Opc);
  463           TII->get(N->getMachineOpcode()).getImplicitDefs()) {
  468         if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
  486         CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
  567   unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
  627         TII->isHighLatencyDef(N->getMachineOpcode()))
  639       SU->Latency += TII->getInstrLatency(InstrItins, N);
  654     OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
  655   int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
  806       BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
  815       BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
  891       TII->insertNoop(*Emitter.getBlock(), InsertPos);

lib/Target/AArch64/AArch64TargetMachine.cpp

  364     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  365     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

  262   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  263   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
  272   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  273   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
  286   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  287   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
  559     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  560     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));

lib/Target/AMDGPU/R600MachineScheduler.cpp

   31   TII = static_cast<const R600InstrInfo*>(DAG->TII);

lib/Target/AMDGPU/SIMachineScheduler.cpp

 1805   SITII = static_cast<const SIInstrInfo*>(TII);

lib/Target/Hexagon/HexagonSubtarget.cpp

  147     auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
  266   const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);

lib/Target/Hexagon/HexagonTargetMachine.cpp

  118   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));

lib/Target/PowerPC/PPCHazardRecognizers.cpp

  282   const MCInstrDesc &MCID = DAG.TII->get(Opcode);

lib/Target/PowerPC/PPCInstrInfo.cpp

  137     assert(DAG->TII && "No InstrInfo?");

lib/Target/PowerPC/PPCTargetMachine.cpp

  275   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));