reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachinePipeliner.h

  335           Latency += Succ.getLatency();

lib/CodeGen/AggressiveAntiDepBreaker.cpp

  286       unsigned PredLatency = P->getLatency();

lib/CodeGen/CriticalAntiDepBreaker.cpp

  152     unsigned PredLatency = P->getLatency();

lib/CodeGen/MachinePipeliner.cpp

 1132     unsigned Lat = D.getLatency();
 1387       if (IP->getLatency() == 0)
 1392       asap = std::max(asap, (int)(getASAP(pred) + IP->getLatency() -
 1411       if (IS->getLatency() == 0)
 1416       alap = std::min(alap, (int)(getALAP(succ) - IS->getLatency() +
 2414             int EarlyStart = cycle + Dep.getLatency() -
 2422             int LateStart = cycle - Dep.getLatency() +
 2438             int LateStart = cycle - Dep.getLatency() +
 2446             int EarlyStart = cycle + Dep.getLatency() -

lib/CodeGen/MachineScheduler.cpp

  636   if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
  637     SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
  673   if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
  674     PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();

lib/CodeGen/ScheduleDAG.cpp

   85     dbgs() << " Latency=" << getLatency();
   91     dbgs() << " Latency=" << getLatency();
   94     dbgs() << " Latency=" << getLatency();
  117       if (PredDep.getLatency() < D.getLatency()) {
  117       if (PredDep.getLatency() < D.getLatency()) {
  124             SuccDep.setLatency(D.getLatency());
  128         PredDep.setLatency(D.getLatency());
  168   if (P.getLatency() != 0) {
  211   if (P.getLatency() != 0) {
  276                                 PredSU->Depth + PredDep.getLatency());
  307                                  SuccSU->Height + SuccDep.getLatency());

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

  414     PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());

lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp

  128   SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());

lib/Target/AMDGPU/GCNILPSched.cpp

  283     PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge.getLatency());

lib/Target/Hexagon/HexagonHazardRecognizer.cpp

  144       if (S.isAssignedRegDep() && S.getLatency() == 0 &&
  159       if (S.isAssignedRegDep() && S.getLatency() == 0 &&

lib/Target/Hexagon/HexagonMachineScheduler.cpp

   86     if (S.getSUnit() == SUu && S.getLatency() > 0)
  294     unsigned MinLatency = PI.getLatency();
  313     unsigned MinLatency = I->getLatency();
  708           PI.getLatency() == 0 &&
  717           SI.getLatency() == 0 &&
  733         if (PI.getLatency() > 0 &&
  741         if (SI.getLatency() > 0 &&

lib/Target/Hexagon/HexagonSubtarget.cpp

  153       if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
  415     Dep.setLatency((Dep.getLatency() + 1) >> 1);
  452     F->setLatency(I.getLatency());
  476     if (I.isAssignedRegDep() && I.getLatency() == 0 &&

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

 1862         if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||
 1872       if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)