reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/TargetInstrInfo.h

  440       return Reg == P.Reg && SubReg == P.SubReg;
  440       return Reg == P.Reg && SubReg == P.SubReg;
 1805     std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
 1812            RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
 1812            RegInfo::isEqual(LHS.SubReg, RHS.SubReg);

lib/CodeGen/PeepholeOptimizer.cpp

  329       return RegSrcs[Idx].SubReg;
  681     ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII);
  731       if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC,
  732                                      CurSrcPair.SubReg))
  737       if (PHICount > 0 && CurSrcPair.SubReg != 0)
  763   assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand");
  771     MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
 1053     if ((Src.SubReg = MOInsertedReg.getSubReg()))
 1058     Dst.SubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
 1115   RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
 1126       LookupSrc.SubReg = Res.getSrcSubReg(0);
 1201     if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) {
 1237           .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
 1239   if (Def.SubReg) {
 1240     NewCopy->getOperand(0).setSubReg(Def.SubReg);
 1913       return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg);
 1950     return ValueTrackerResult(InsertedReg.Reg, InsertedReg.SubReg);
 1960       BaseReg.SubReg)
 1997   if (ExtractSubregInputReg.SubReg)

lib/CodeGen/TailDuplicator.cpp

  406           if (VI->second.SubReg != 0) {
  408                                                      VI->second.SubReg);
  428                                                    VI->second.SubReg));
  439                 .addReg(VI->second.Reg, 0, VI->second.SubReg);
  985                 .addReg(CI.second.Reg, 0, CI.second.SubReg);

lib/CodeGen/TargetInstrInfo.cpp

 1213   InputReg.SubReg = MOReg.getSubReg();
 1238   BaseReg.SubReg = MOBaseReg.getSubReg();
 1241   InsertedReg.SubReg = MOInsertedReg.getSubReg();

lib/Target/AMDGPU/GCNDPPCombine.cpp

  182                      CombOldVGPR.SubReg);

lib/Target/AMDGPU/SIFoldOperands.cpp

  721                        Src.SubReg);

lib/Target/AMDGPU/SIInstrInfo.cpp

 6393   if (!RSR.SubReg)
 6398     RSR = getRegSequenceSubReg(MI, RSR.SubReg);
 6402     if (RSR.SubReg == (unsigned)MI.getOperand(3).getImm())
 6407       if (R1.SubReg) // subreg of subreg isn't supported

lib/Target/AMDGPU/SIInstrInfo.h

 1037   if (!P.SubReg)
 1040   return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  530         .addDef(X1.Reg, 0, X1.SubReg)
  531         .addDef(Y1.Reg, 0, Y1.SubReg)
  532         .addReg(Y1.Reg, 0, Y1.SubReg)
  533         .addReg(X1.Reg, 0, X1.SubReg).getInstr();

lib/Target/ARM/ARMBaseInstrInfo.cpp

 5292     InputReg.SubReg = MOReg.getSubReg();
 5314     BaseReg.SubReg = MOBaseReg.getSubReg();
 5317     InsertedReg.SubReg = MOInsertedReg.getSubReg();