reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/CalcSpillWeights.cpp

   79     return tri.getMatchingSuperReg(CopiedPReg, sub, rc);

lib/CodeGen/RegisterCoalescer.cpp

  429       Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));

lib/CodeGen/TwoAddressInstructionPass.cpp

 1566         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))

lib/Target/AArch64/AArch64InstrInfo.cpp

 2474         unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
 2476         unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
 2500         unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
 2502         unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
 2662       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
 2664       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
 2679       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
 2681       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
 2696       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
 2698       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
 2704       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
 2706       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
 2717       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
 2719       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
 2725       DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
 2727       SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
 3303                 TRI.getMatchingSuperReg(SrcReg, SpillSubreg, SpillRC)) {

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

 1001         IsStoreXReg ? Register(TRI->getMatchingSuperReg(

lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp

  310           DstMI = TRI->getMatchingSuperReg(Reg,
  319           SrcMI = TRI->getMatchingSuperReg(Reg,

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

  191     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  198   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  205   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  213     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  220   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  227   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  234   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(

lib/Target/AMDGPU/SIRegisterInfo.cpp

  113   return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass);

lib/Target/ARM/A15SDOptimizer.cpp

  145   unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,

lib/Target/ARM/ARMBaseInstrInfo.cpp

 1596   unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
 1598   unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
 4873   unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
 4880   DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
 5184     unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,

lib/Target/ARM/ARMExpandPseudoInsts.cpp

  496     unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,

lib/Target/ARM/ARMFrameLowering.cpp

 1241     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
 1260     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
 1275     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
 1373     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
 1391     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
 1404     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,

lib/Target/Hexagon/HexagonCopyToCombine.cpp

  600   unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);

lib/Target/PowerPC/PPCISelLowering.cpp

14377     return std::make_pair(TRI->getMatchingSuperReg(R.first,

lib/Target/PowerPC/PPCInstrInfo.cpp

  914       TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
  923       TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);

lib/Target/SystemZ/SystemZInstrInfo.cpp

  795       RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
  798       RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
  809       RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
  812       RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),

lib/Target/SystemZ/SystemZRegisterInfo.cpp

  178             PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),

lib/Target/SystemZ/SystemZShortenInst.cpp

   88       TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);

lib/Target/X86/X86InstrInfo.cpp

 3002       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
 3004       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
 3017       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
 3019       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
 4033     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
 4056     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
 4127         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
 4147         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);