reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

72556   int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);

lib/CodeGen/PrologEpilogInserter.cpp

  433       unsigned Size = RegInfo->getSpillSize(*RC);

lib/CodeGen/RegAllocFast.cpp

  256   unsigned Size = TRI->getSpillSize(RC);

lib/CodeGen/RegisterScavenging.cpp

  467   unsigned NeedSize = TRI->getSpillSize(RC);

lib/CodeGen/StackMaps.cpp

  163     Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC),
  249   unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg));

lib/CodeGen/TargetInstrInfo.cpp

  384     Size = TRI->getSpillSize(*RC);
  400   assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
  403     Offset = TRI->getSpillSize(*RC) - (Offset + Size);

lib/CodeGen/TargetLoweringBase.cpp

 1152     if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
 1152     if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))

lib/CodeGen/VirtRegMap.cpp

   94   unsigned Size = TRI->getSpillSize(*RC);

lib/Target/AArch64/AArch64FrameLowering.cpp

 2292       unsigned Size = TRI->getSpillSize(RC);

lib/Target/AArch64/AArch64InstrInfo.cpp

 2818   switch (TRI->getSpillSize(*RC)) {
 2949   switch (TRI->getSpillSize(*RC)) {

lib/Target/AMDGPU/SIFrameLowering.cpp

  972         TRI->getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
  976         TRI->getSpillSize(AMDGPU::SGPR_32RegClass),

lib/Target/AMDGPU/SIISelLowering.cpp

 2482     EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;

lib/Target/AMDGPU/SIInstrInfo.cpp

 1061   unsigned SpillSize = TRI->getSpillSize(*RC);
 1183   unsigned SpillSize = TRI->getSpillSize(*RC);

lib/Target/AMDGPU/SILowerSGPRSpills.cpp

  209         int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),

lib/Target/ARC/ARCFrameLowering.cpp

  445         RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false);

lib/Target/ARC/ARCInstrInfo.cpp

  309   assert(TRI->getSpillSize(*RC) == 4 &&
  336   assert(TRI->getSpillSize(*RC) == 4 &&

lib/Target/ARM/ARMBaseInstrInfo.cpp

 1040   switch (TRI->getSpillSize(*RC)) {
 1282   switch (TRI->getSpillSize(*RC)) {

lib/Target/ARM/ARMFrameLowering.cpp

 2119         unsigned Size = TRI->getSpillSize(RC);

lib/Target/Hexagon/HexagonFrameLowering.cpp

 1517     int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
 1529     unsigned Size = TRI->getSpillSize(*RC);
 1754   unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 1801   unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 1965       unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC);

lib/Target/Hexagon/HexagonInstrInfo.cpp

 1096       unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 1118       unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
 2697     unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
 4214       return HRI.getSpillSize(Hexagon::HvxVRRegClass);

lib/Target/Hexagon/HexagonVExtract.cpp

  125     int FI = MFI.CreateSpillStackObject(HRI.getSpillSize(VecRC),

lib/Target/Mips/MipsFrameLowering.cpp

  127     unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));

lib/Target/Mips/MipsMachineFunction.cpp

  158     EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
  173         TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false);
  196         TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);

lib/Target/Mips/MipsSEFrameLowering.cpp

  897     int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
  914   int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),

lib/Target/PowerPC/PPCFrameLowering.cpp

 2111     unsigned Size = TRI.getSpillSize(RC);

lib/Target/RISCV/RISCVFrameLowering.cpp

  426         RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false);

lib/Target/X86/X86FrameLowering.cpp

 1560                      TRI->getSpillSize(X86::VR128RegClass);
 2042     unsigned Size = TRI->getSpillSize(*RC);

lib/Target/X86/X86InstrInfo.cpp

 3069   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
 3250   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
 3252   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
 3267   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
 5410   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
 5504       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
 5581     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
 5648       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
 5714     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);

lib/Target/XCore/XCoreFrameLowering.cpp

  584   unsigned Size = TRI.getSpillSize(RC);

lib/Target/XCore/XCoreMachineFunctionInfo.cpp

   43     LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true);
   45     LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC),
   59   FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC),
   72   unsigned Size = TRI.getSpillSize(RC);