reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/MC/MCInstrDesc.h

  102     return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
  103            OperandType <= MCOI::OPERAND_LAST_GENERIC;
  108     return OperandType - MCOI::OPERAND_FIRST_GENERIC;
  112     return OperandType >= MCOI::OPERAND_FIRST_GENERIC_IMM &&
  113            OperandType <= MCOI::OPERAND_LAST_GENERIC_IMM;
  118     return OperandType - MCOI::OPERAND_FIRST_GENERIC_IMM;

lib/MC/MCInstrAnalysis.cpp

   29       Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

  319       if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 1712   uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType;
 2759     const unsigned OperandType = Desc.OpInfo[OpIdx].OperandType;
 2859           if (Desc.OpInfo[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)
 6185   return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS

lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

  520     switch (Desc.OpInfo[OpNo].OperandType) {

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

  118         Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

  236   switch (OpInfo.OperandType) {

lib/Target/AMDGPU/SIFoldOperands.cpp

  161       return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
  217       switch (TII.get(Opcode).OpInfo[OpNo].OperandType) {
  491   uint8_t OpTy = OpInfo[UseOpIdx].OperandType;

lib/Target/AMDGPU/SIInstrInfo.cpp

 2931   if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
 2945     return RI.opCanUseInlineConstant(OpInfo.OperandType);
 2948   if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
 3243     switch (Desc.OpInfo[i].OperandType) {
 3534         !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
 3537         !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
 3983       } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {

lib/Target/AMDGPU/SIInstrInfo.h

  699     return isInlineConstant(MO, OpInfo.OperandType);
  720     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
  737     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
  747     return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
  808       assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 1041   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
 1048   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
 1072   unsigned OpType = Desc.OpInfo[OpNo].OperandType;

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

  580   switch (OpInfo.OperandType) {

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 7285     if (ARM::isVpred(MCID.OpInfo[i].OperandType))

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

  749     if (ARM::isVpred(OpInfo[i].OperandType))
  846     if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
  856     if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

  268     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
  298     if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=

lib/Target/ARM/Thumb2InstrInfo.cpp

  712     if (ARM::isVpred(MCID.OpInfo[i].OperandType))

lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp

  101     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType ==

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 2074       if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
 2075           (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
 2108         if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
 2109             (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

  145     switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {

lib/Target/RISCV/RISCVInstrInfo.cpp

  497     unsigned OpType = OI.value().OperandType;

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp

  158           if (Desc.OpInfo[I].OperandType != WebAssembly::OPERAND_BASIC_BLOCK)
  229     if (Info.OperandType == WebAssembly::OPERAND_F32IMM) {
  234       assert(Info.OperandType == WebAssembly::OPERAND_F64IMM);

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp

   93                           << int(Info.OperandType) << "\n");
   94         switch (Info.OperandType) {
  130       if (Info.OperandType == WebAssembly::OPERAND_F32IMM) {
  136         assert(Info.OperandType == WebAssembly::OPERAND_F64IMM);
  145       switch (Info.OperandType) {

lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp

  235         if (Info.OperandType == WebAssembly::OPERAND_TYPEINDEX) {
  259         } else if (Info.OperandType == WebAssembly::OPERAND_SIGNATURE) {

lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp

   65   assert(MI.getDesc().OpInfo[OperandNo].OperandType ==

tools/llvm-exegesis/lib/MCInstrDescView.cpp

   62          getExplicitOperandInfo().OperandType == MCOI::OPERAND_MEMORY;
   67          getExplicitOperandInfo().OperandType == MCOI::OPERAND_IMMEDIATE;

tools/llvm-exegesis/lib/Target.cpp

   94   switch (Op.getExplicitOperandInfo().OperandType) {

tools/llvm-exegesis/lib/X86/Target.cpp

  163         Op.getExplicitOperandInfo().OperandType == MCOI::OPERAND_PCREL)
  620   switch (Op.getExplicitOperandInfo().OperandType) {

unittests/Target/ARM/MachineInstrTest.cpp

  495       if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||