reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/TargetInstrInfo.cpp

   51   short RegClass = MCID.OpInfo[OpNum].RegClass;

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

  518   unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  570     int RegClass = Desc.OpInfo[OpIdx].RegClass;

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 6189       && Desc.OpInfo[OpNum + 1].RegClass != -1

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

  551     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
  574     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

  680     VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
  705            AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256);
  711     if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)

lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

  578       int RCID = Desc.OpInfo[OpNo].RegClass;

lib/Target/AMDGPU/SIFoldOperands.cpp

  826         UseDesc.OpInfo[UseOpIdx].RegClass == -1)
  842     TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);

lib/Target/AMDGPU/SIISelLowering.cpp

10407         if ((OpInfo[I].RegClass != llvm::AMDGPU::AV_64RegClassID &&
10408              OpInfo[I].RegClass != llvm::AMDGPU::AV_32RegClassID) ||

lib/Target/AMDGPU/SIInstrInfo.cpp

 2934   if (OpInfo.RegClass < 0)
 3241     int RegClass = Desc.OpInfo[i].RegClass;
 3812       Desc.OpInfo[OpNo].RegClass == -1) {
 3820   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
 3831   unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
 3924   const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
 3957       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
 3957       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
 4671     unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
 5814     const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
 6265   const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;

lib/Target/AMDGPU/SIInstrInfo.h

  806     if (OpInfo.RegClass == -1) {
  812     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
 1026     return RI.getRegClass(TID.OpInfo[OpNum].RegClass);

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

 1182     if (Desc.OpInfo[I].RegClass == -1 ||
 1183        !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass)))

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 1135   unsigned RCID = Desc.OpInfo[OpNo].RegClass;

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

10268     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

  735     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {

lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp

  106     bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) ||
  107                     (MOI.RegClass == AVR::PTRDISPREGSRegClassID) ||
  108                     (MOI.RegClass == AVR::ZREGRegClassID);

lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp

  456     if (Desc.OpInfo[std::get<1>(Producer)].RegClass ==

lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp

  822     if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 3609   int16_t DstRegClass = Desc.OpInfo[0].RegClass;

lib/Target/PowerPC/PPCInstrInfo.cpp

 1360     if (UseInfo->RegClass /* Kind */ != 1)
 1363     if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
 1364         UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
 1379     ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?

lib/Target/PowerPC/PPCInstrInfo.h

  469     int16_t regClass = Desc.OpInfo[OpNo].RegClass;

lib/Target/X86/X86MCInstLower.cpp

 1819   if (Info.RegClass == X86::VR128RegClassID ||
 1820       Info.RegClass == X86::VR128XRegClassID)
 1822   if (Info.RegClass == X86::VR256RegClassID ||
 1823       Info.RegClass == X86::VR256XRegClassID)
 1825   if (Info.RegClass == X86::VR512RegClassID)

tools/llvm-exegesis/lib/MCInstrDescView.cpp

  108     if (OpInfo.RegClass >= 0)
  109       Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);
  250                       &RegInfo.getRegClass(Op.Info->RegClass))

tools/llvm-exegesis/lib/X86/Target.cpp

  169         Op.getExplicitOperandInfo().RegClass == X86::RSTRegClassID)

unittests/Target/ARM/MachineInstrTest.cpp

  496           Op.RegClass != ARM::MQPRRegClassID)