reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/DFAPacketizer.cpp

  106   unsigned InsnClass = MID->getSchedClass();
  114   unsigned InsnClass = MID->getSchedClass();

lib/CodeGen/MachineCombiner.cpp

  362     unsigned Idx = TII->get(Opc).getSchedClass();

lib/CodeGen/MachinePipeliner.cpp

  917     unsigned SchedClass = Inst->getDesc().getSchedClass();
  964     unsigned SchedClass = MI.getDesc().getSchedClass();
 2941   unsigned InsnClass = MID->getSchedClass();
 2981   unsigned InsnClass = MID->getSchedClass();

lib/CodeGen/ScoreboardHazardRecognizer.cpp

  127   unsigned idx = MCID->getSchedClass();
  186   unsigned idx = MCID->getSchedClass();

lib/CodeGen/TargetInstrInfo.cpp

 1047   unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
 1050   unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
 1062   return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
 1074   unsigned Class = MI.getDesc().getSchedClass();
 1108   return ItinData->getStageLatency(MI.getDesc().getSchedClass());
 1118   unsigned DefClass = DefMI.getDesc().getSchedClass();
 1145   unsigned DefClass = DefMI.getDesc().getSchedClass();
 1146   unsigned UseClass = UseMI.getDesc().getSchedClass();

lib/CodeGen/TargetSchedule.cpp

  110     int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
  135   unsigned SchedClass = MI->getDesc().getSchedClass();
  198       unsigned DefClass = DefMI->getDesc().getSchedClass();
  262   unsigned SCIdx = TII->get(Opcode).getSchedClass();
  327     unsigned SchedClass = MI->getDesc().getSchedClass();
  340   unsigned SchedClass = TII->get(Opcode).getSchedClass();

lib/MC/MCDisassembler/Disassembler.cpp

  181   unsigned SCClass = Desc.getSchedClass();
  208   unsigned SCClass = Desc.getSchedClass();

lib/MC/MCSchedule.cpp

   70   unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
  113   unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();

lib/MCA/InstrBuilder.cpp

  519   unsigned SchedClassID = MCDesc.getSchedClass();

lib/Target/AArch64/AArch64SIMDInstrOpt.cpp

  227   unsigned SCIdx = InstDesc->getSchedClass();
  242       IDesc->getSchedClass());

lib/Target/AArch64/AArch64StorePairSuppress.cpp

   85   unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();

lib/Target/AMDGPU/R600InstrInfo.cpp

  180   return (get(Opcode).getSchedClass() == R600::Sched::TransALU);
  188   return (get(Opcode).getSchedClass() == R600::Sched::VecALU);

lib/Target/ARM/ARMBaseInstrInfo.cpp

 3337     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
 3640   unsigned Class = Desc.getSchedClass();
 3914   unsigned DefClass = DefMCID.getSchedClass();
 3915   unsigned UseClass = UseMCID.getSchedClass();
 4365     int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
 4657   unsigned Class = MCID.getSchedClass();
 4687     return ItinData->getStageLatency(get(Opcode).getSchedClass());
 4724     unsigned DefClass = DefMI.getDesc().getSchedClass();

lib/Target/ARM/ARMISelLowering.cpp

 1752       Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)

lib/Target/Hexagon/HexagonInstrInfo.cpp

 2152   unsigned SchedClass = MI.getDesc().getSchedClass();
 2344   unsigned SchedClass = MI.getDesc().getSchedClass();
 2593   unsigned SchedClass = MI.getDesc().getSchedClass();
 2598   unsigned SchedClass = MI.getDesc().getSchedClass();
 2603   unsigned SchedClass = MI.getDesc().getSchedClass();
 2608   unsigned SchedClass = MI.getDesc().getSchedClass();
 4082   return ItinData->getStageLatency(MI.getDesc().getSchedClass());
 4332   const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
 4399                       << "  Class: " << NewMI->getDesc().getSchedClass());

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

 1053   auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());

lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp

  402   int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
  413   int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();

lib/Target/PowerPC/PPCHazardRecognizers.cpp

   66     if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
   90   unsigned IIC = MCID->getSchedClass();

lib/Target/PowerPC/PPCInstrInfo.cpp

  159   unsigned DefClass = MI.getDesc().getSchedClass();

tools/llvm-exegesis/lib/SchedClassResolution.cpp

  233   unsigned SchedClassId = InstrInfo.get(MCI.getOpcode()).getSchedClass();

tools/llvm-exegesis/llvm-exegesis.cpp

  255           State.getInstrInfo().get(Opcode).getSchedClass() == 0) {

tools/llvm-mca/Views/InstructionInfoView.cpp

   44     unsigned SchedClassID = MCDesc.getSchedClass();