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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenCallingConv.inc 437 if (LocVT == MVT::i128) {
608 if (LocVT == MVT::i128) {
729 if (LocVT == MVT::i128) {
include/llvm/Support/MachineValueType.h 48 LAST_INTEGER_VALUETYPE = i128,
507 case v1i128: return i128;
752 case i128:
894 return MVT::i128;
961 case MVT::i128:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 3500 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2151 case MVT::i128: LC = Call_I128; break;
2194 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
4096 case MVT::i128:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 1568 } else if (SrcVT.bitsLE(MVT::i128)) {
1569 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
1602 case MVT::i128:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 2790 else if (VT == MVT::i128)
3144 else if (VT == MVT::i128)
3222 else if (VT == MVT::i128)
3232 else if (VT == MVT::i128)
3243 else if (VT == MVT::i128)
3335 else if (VT == MVT::i128)
3425 else if (VT == MVT::i128)
3493 else if (VT == MVT::i128)
3520 else if (VT == MVT::i128)
4008 else if (SrcVT == MVT::i128)
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4317 if (VT == MVT::f128 && C->getValueType(0) == MVT::i128)
lib/CodeGen/SelectionDAG/TargetLowering.cpp 7239 else if (WideVT == MVT::i128)
lib/CodeGen/TargetLoweringBase.cpp 283 if (RetVT == MVT::i128)
290 if (RetVT == MVT::i128)
297 if (RetVT == MVT::i128)
304 if (RetVT == MVT::i128)
311 if (RetVT == MVT::i128)
325 if (RetVT == MVT::i128)
332 if (RetVT == MVT::i128)
339 if (RetVT == MVT::i128)
346 if (RetVT == MVT::i128)
353 if (RetVT == MVT::i128)
384 } else if (OpVT == MVT::i128) {
424 } else if (OpVT == MVT::i128) {
458 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
459 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
460 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
461 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
462 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
463 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
464 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
465 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
466 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
467 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
468 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
469 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
1215 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1216 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1217 TransformToType[MVT::ppcf128] = MVT::i128;
1225 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1226 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1227 TransformToType[MVT::f128] = MVT::i128;
lib/CodeGen/ValueTypes.cpp 128 case MVT::i128: return "i128";
275 case MVT::i128: return IntegerType::get(Context, 128);
lib/Target/AArch64/AArch64ISelLowering.cpp 263 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
266 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
269 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
272 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
507 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
2548 if (Op.getOperand(0).getValueType() == MVT::i128)
8440 Info.memVT = MVT::i128;
8449 Info.memVT = MVT::i128;
11962 DAG.getNode(ISD::SRL, DL, MVT::i128, N,
11972 DAG.getNode(ISD::SRL, dl, MVT::i128, V, DAG.getConstant(64, dl, MVT::i64)),
11989 assert(N->getValueType(0) == MVT::i128 &&
12090 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 793 if (N->getValueType(0) == MVT::i128) {
lib/Target/AMDGPU/SIISelLowering.cpp10633 if (RC && (isTypeLegal(VT) || VT.SimpleTy == MVT::i128 ||
lib/Target/ARM/ARMFastISel.cpp 1713 else if (VT == MVT::i128)
1742 else if (VT == MVT::i128)
lib/Target/AVR/AVRISelLowering.cpp 363 case MVT::i128:
lib/Target/PowerPC/PPCISelLowering.cpp 911 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
15292 if (Op0.getValueType() != MVT::i128 || N->getValueType(0) != MVT::i64)
15312 Op0.getValueType() == MVT::i128 &&
lib/Target/Sparc/SparcISelLowering.cpp 1080 IReg, MVT::i128, CCValAssign::BCvt);
1160 || VA.getLocVT() != MVT::i128)
1167 && VA.getLocVT() == MVT::i128) {
2940 EVT WideVT = MVT::i128;
lib/Target/SystemZ/SystemZISelLowering.cpp 235 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
236 setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);
242 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
1080 else if (VT == MVT::i128)
1087 else if (VT == MVT::i128)
1121 if (VT == MVT::i128)
1649 if (Out.ArgVT == MVT::i128)
5063 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128, Lo, Hi);
5077 DL, Tys, Ops, MVT::i128, MMO);
5090 DL, Tys, Ops, MVT::i128, MMO);
5108 DL, Tys, Ops, MVT::i128, MMO);
lib/Target/X86/X86ISelLowering.cpp 480 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
1816 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1817 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1818 setOperationAction(ISD::SREM, MVT::i128, Custom);
1819 setOperationAction(ISD::UREM, MVT::i128, Custom);
1820 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1821 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
28279 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
28280 bool Regs64bit = T == MVT::i128;
utils/TableGen/CodeGenTarget.cpp 66 case MVT::i128: return "MVT::i128";