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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenCallingConv.inc 154 LocVT == MVT::nxv8f16 ||
175 LocVT == MVT::nxv8f16 ||
1164 LocVT == MVT::nxv8f16 ||
gen/lib/Target/AArch64/AArch64GenDAGISel.inc82358 /*191443*/ OPC_CheckChild3Type, MVT::nxv8f16,
101581 /*227691*/ /*SwitchType*/ 5, MVT::nxv8f16,// ->227698
101614 /*227738*/ /*SwitchType*/ 5, MVT::nxv8f16,// ->227745
101647 /*227785*/ /*SwitchType*/ 5, MVT::nxv8f16,// ->227792
101664 /*227808*/ OPC_CheckChild0Type, MVT::nxv8f16,
101718 /*227886*/ /*SwitchType*/ 5, MVT::nxv8f16,// ->227893
101751 /*227933*/ /*SwitchType*/ 5, MVT::nxv8f16,// ->227940
101779 /*227973*/ /*SwitchType*/ 5, MVT::nxv8f16,// ->227980
104781 /*234601*/ /*SwitchType*/ 10, MVT::nxv8f16,// ->234613
104784 MVT::nxv8f16, 2/*#Ops*/, 0, 1,
111844 /*249681*/ /*SwitchType*/ 18, MVT::nxv8f16,// ->249701
111850 MVT::nxv8f16, 3/*#Ops*/, 2, 1, 4,
gen/lib/Target/AArch64/AArch64GenFastISel.inc 6231 if (RetVT.SimpleTy != MVT::nxv8f16)
6267 case MVT::nxv8f16: return fastEmit_ISD_FADD_MVT_nxv8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 5187 /* 39 */ MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64, MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv1f32, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv1f64, MVT::nxv2f64, MVT::Other,
include/llvm/Support/MachineValueType.h 516 case nxv8f16: return f16;
611 case nxv8f16:
766 case nxv8f16:
1045 if (NumElements == 8) return MVT::nxv8f16;
lib/CodeGen/ValueTypes.cpp 245 case MVT::nxv8f16: return "nxv8f16";
421 case MVT::nxv8f16:
lib/Target/AArch64/AArch64ISelLowering.cpp 180 addRegisterClass(MVT::nxv8f16, &AArch64::ZPRRegClass);
utils/TableGen/CodeGenTarget.cpp 183 case MVT::nxv8f16: return "MVT::nxv8f16";