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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc35211 MVT::v32f32, 6/*#Ops*/, 0, 1, 2, 3, 4, 5,
35255 MVT::v32f32, 6/*#Ops*/, 0, 1, 2, 3, 4, 5,
35299 MVT::v32f32, 6/*#Ops*/, 0, 1, 2, 3, 4, 5,
59204 /*129593*/ OPC_CheckChild0Type, MVT::v32f32,
62806 /*137062*/ OPC_CheckChild0Type, MVT::v32f32,
62843 /*137111*/ OPC_CheckType, MVT::v32f32,
77920 /*173248*/ /*SwitchType*/ 12, MVT::v32f32,// ->173262
77923 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
77965 /*173351*/ /*SwitchType*/ 12, MVT::v32f32,// ->173365
77968 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78010 /*173454*/ /*SwitchType*/ 12, MVT::v32f32,// ->173468
78013 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78043 /*173529*/ /*SwitchType*/ 12, MVT::v32f32,// ->173543
78046 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78070 /*173590*/ /*SwitchType*/ 12, MVT::v32f32,// ->173604
78073 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78091 /*173637*/ /*SwitchType*/ 12, MVT::v32f32,// ->173651
78094 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78112 /*173684*/ /*SwitchType*/ 12, MVT::v32f32,// ->173698
78115 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78133 /*173731*/ /*SwitchType*/ 12, MVT::v32f32,// ->173745
78136 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78148 /*173764*/ /*SwitchType*/ 12, MVT::v32f32,// ->173778
78151 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78163 /*173797*/ /*SwitchType*/ 12, MVT::v32f32,// ->173811
78166 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78178 /*173830*/ /*SwitchType*/ 12, MVT::v32f32,// ->173844
78181 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78193 /*173863*/ /*SwitchType*/ 12, MVT::v32f32,// ->173877
78196 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78208 /*173896*/ /*SwitchType*/ 12, MVT::v32f32,// ->173910
78211 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78223 /*173929*/ /*SwitchType*/ 12, MVT::v32f32,// ->173943
78226 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78238 /*173962*/ /*SwitchType*/ 12, MVT::v32f32,// ->173976
78241 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78253 /*173995*/ /*SwitchType*/ 12, MVT::v32f32,// ->174009
78256 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78262 /*174013*/ OPC_CheckType, MVT::v32f32,
78265 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78270 /*174030*/ OPC_CheckType, MVT::v32f32,
78273 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78278 /*174047*/ OPC_CheckType, MVT::v32f32,
78281 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78286 /*174064*/ OPC_CheckType, MVT::v32f32,
78289 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78294 /*174081*/ OPC_CheckType, MVT::v32f32,
78297 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78302 /*174098*/ OPC_CheckType, MVT::v32f32,
78305 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78310 /*174115*/ OPC_CheckType, MVT::v32f32,
78313 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78318 /*174132*/ OPC_CheckType, MVT::v32f32,
78321 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78326 /*174149*/ OPC_CheckType, MVT::v32f32,
78329 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78334 /*174166*/ OPC_CheckType, MVT::v32f32,
78337 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78342 /*174183*/ OPC_CheckType, MVT::v32f32,
78345 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78350 /*174200*/ OPC_CheckType, MVT::v32f32,
78353 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78358 /*174217*/ OPC_CheckType, MVT::v32f32,
78361 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78366 /*174234*/ OPC_CheckType, MVT::v32f32,
78369 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78374 /*174251*/ OPC_CheckType, MVT::v32f32,
78377 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
78382 /*174268*/ OPC_CheckType, MVT::v32f32,
78385 MVT::v32f32, 3/*#Ops*/, 0, 1, 2,
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17476 /* 94 */ MVT::v32i32, MVT::v32f32, MVT::Other,
include/llvm/Support/MachineValueType.h 524 case v32f32:
579 case v32f32:
803 case v32f32:
980 if (NumElements == 32) return MVT::v32f32;
lib/CodeGen/ValueTypes.cpp 202 case MVT::v32f32: return "v32f32";
346 case MVT::v32f32: return VectorType::get(Type::getFloatTy(Context), 32);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 91 setOperationAction(ISD::LOAD, MVT::v32f32, Promote);
92 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32);
158 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand);
191 setOperationAction(ISD::STORE, MVT::v32f32, Promote);
192 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32);
222 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand);
298 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom);
lib/Target/AMDGPU/SIISelLowering.cpp 158 addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
251 MVT::v32i32, MVT::v32f32 }) {
utils/TableGen/CodeGenTarget.cpp 142 case MVT::v32f32: return "MVT::v32f32";