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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc39047 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39052 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
39072 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39076 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
39095 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39116 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39137 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39178 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
39216 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG,
39248 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG,
39278 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39310 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39350 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39382 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39426 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
39454 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39486 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39652 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39657 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
39676 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39680 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
39698 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39719 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39740 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39781 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
39819 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG,
39841 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39873 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
39909 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
39937 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40023 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40028 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
40047 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40051 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
40069 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40090 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40111 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40148 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40169 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40212 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40233 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40278 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40320 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40341 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40386 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc18833 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
18895 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
gen/lib/Target/ARM/ARMGenGlobalISel.inc25891 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
25912 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
25955 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
25976 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26187 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26192 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
26213 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26236 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26259 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26306 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26311 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
26332 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26355 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26378 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26425 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26498 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
26697 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
26726 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
26819 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
26848 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc11531 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11536 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
11556 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11561 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
11581 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11586 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
11606 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11627 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11648 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11671 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11692 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11713 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11741 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11746 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
11766 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11771 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
11791 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11796 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
11816 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11837 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11858 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11881 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11902 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
11923 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 314 inline UnaryOp_match<SrcTy, TargetOpcode::G_FNEG> m_GFNeg(const SrcTy &Src) {
315 return UnaryOp_match<SrcTy, TargetOpcode::G_FNEG>(Src);
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 1399 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
lib/CodeGen/GlobalISel/IRTranslator.cpp 318 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op1}, Flags);
332 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op0}, Flags);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 1826 case TargetOpcode::G_FNEG:
1975 case TargetOpcode::G_FNEG: {
2013 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2019 MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
2963 case G_FNEG:
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 281 setScalarAction(TargetOpcode::G_FNEG, 0, {{1, Lower}});
lib/Target/AArch64/AArch64LegalizerInfo.cpp 148 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG})
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 400 case TargetOpcode::G_FNEG:
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 385 getActionDefinitionsBuilder({G_FNEG, G_FABS})
lib/Target/ARM/ARMLegalizerInfo.cpp 173 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
201 setAction({G_FNEG, Ty}, Lower);
lib/Target/ARM/ARMRegisterBankInfo.cpp 291 case G_FNEG: {
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 768 B.buildInstr(TargetOpcode::G_FNEG, {LLT::scalar(64)}, {FAdd.getReg(0)},
773 B.buildInstr(TargetOpcode::G_FNEG, {LLT::scalar(64)}, {Copies[0]},
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 148 auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32});