reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenGlobalISel.inc
 1320         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1355         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1405         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1440         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1474         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1503         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1533         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1562         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1959         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1981         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 2605         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 2627         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3081         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3139         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3305         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3327         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3781         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3839         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4005         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4027         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4078         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4173         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4208         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4243         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4272         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4301         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4336         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4371         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4400         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4429         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4536         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4718         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4846         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4921         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 5049         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 5124         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc
  539         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
  558         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
  577         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
gen/lib/Target/ARM/ARMGenGlobalISel.inc
 1089         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1125         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1162         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1198         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1301         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1326         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1351         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1424         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1449         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1474         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1727         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1751         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 2165         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 2189         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 2509         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 2576         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 2786         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 2810         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3130         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3197         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3411         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3436         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3632         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3656         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3744         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3902         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 3998         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4109         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4205         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 4316         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
gen/lib/Target/Mips/MipsGenGlobalISel.inc
  964         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
  986         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1038         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1060         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1098         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1120         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1158         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1180         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1336         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1388         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1426         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1464         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
12543         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
gen/lib/Target/X86/X86GenGlobalISel.inc
 1234         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1257         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1347         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
 1370         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h
   38     case TargetOpcode::G_MUL:
include/llvm/CodeGen/GlobalISel/IRTranslator.h
  363     return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
  206 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>
  208   return BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>(L, R);
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
 1261     return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
lib/CodeGen/GlobalISel/CSEInfo.cpp
   39   case TargetOpcode::G_MUL:
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
  148   case TargetOpcode::G_MUL:
lib/CodeGen/GlobalISel/GISelKnownBits.cpp
  236   case TargetOpcode::G_MUL: {
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  786   case TargetOpcode::G_MUL:
 1535   case TargetOpcode::G_MUL:
 2957   case G_MUL:
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  970   case TargetOpcode::G_MUL:
lib/CodeGen/GlobalISel/Utils.cpp
  358     case TargetOpcode::G_MUL:
lib/Target/AArch64/AArch64InstructionSelector.cpp
 4211   if (OffsetOpc != TargetOpcode::G_SHL && OffsetOpc != TargetOpcode::G_MUL)
 4242   if (OffsetOpc == TargetOpcode::G_MUL) {
lib/Target/AArch64/AArch64LegalizerInfo.cpp
   88   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
  533   case TargetOpcode::G_MUL:
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  264     getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
  269     getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
lib/Target/ARM/ARMLegalizerInfo.cpp
   89   getActionDefinitionsBuilder({G_MUL, G_AND, G_OR, G_XOR})
lib/Target/ARM/ARMRegisterBankInfo.cpp
  240   case G_MUL:
lib/Target/Mips/MipsLegalizerInfo.cpp
   64   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
  403     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
lib/Target/Mips/MipsRegisterBankInfo.cpp
  458   case G_MUL:
lib/Target/X86/X86LegalizerInfo.cpp
   74   for (unsigned BinOp : {G_SUB, G_MUL, G_AND, G_OR, G_XOR})
  122   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
  219   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
  337   setAction({G_MUL, v8s16}, Legal);
  366   setAction({G_MUL, v4s32}, Legal);
  431     setAction({G_MUL, Ty}, Legal);
  467   setAction({G_MUL, v16s32}, Legal);
  487     setAction({G_MUL, Ty}, Legal);
  496   setAction({G_MUL, v8s64}, Legal);
  506     setAction({G_MUL, Ty}, Legal);
  520   setAction({G_MUL, v32s16}, Legal);
  530     setAction({G_MUL, Ty}, Legal);
lib/Target/X86/X86RegisterBankInfo.cpp
  177   case TargetOpcode::G_MUL:
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp
  132       ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
  137       ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),