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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1324 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1409 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1478 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1482 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
1537 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1541 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
2299 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2303 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2343 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2380 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3037 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3041 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3102 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3160 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3737 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3741 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3802 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3860 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4177 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4247 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4251 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
4305 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4375 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4379 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT,
4619 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4623 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4664 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4801 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4805 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4867 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
5004 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
5008 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
5070 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
5274 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
5330 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
5334 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
37548 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
37589 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
37694 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
37753 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
37858 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
37898 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
37954 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
gen/lib/Target/ARM/ARMGenGlobalISel.inc 1913 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1917 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1961 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2002 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2459 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2463 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2533 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2600 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3080 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3084 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3154 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3221 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3789 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3793 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3838 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3947 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3951 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4022 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4154 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4158 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4229 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
include/llvm/CodeGen/GlobalISel/IRTranslator.h 415 return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 34 case TargetOpcode::G_SEXT:
136 assert(MI.getOpcode() == TargetOpcode::G_SEXT);
191 Opcode == TargetOpcode::G_SEXT);
442 case TargetOpcode::G_SEXT:
468 case TargetOpcode::G_SEXT:
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 265 inline UnaryOp_match<SrcTy, TargetOpcode::G_SEXT> m_GSExt(const SrcTy &Src) {
266 return UnaryOp_match<SrcTy, TargetOpcode::G_SEXT>(Src);
lib/CodeGen/GlobalISel/CSEInfo.cpp 51 case TargetOpcode::G_SEXT:
lib/CodeGen/GlobalISel/CombinerHelper.cpp 295 if (CurrentUse.ExtendOpcode == TargetOpcode::G_SEXT &&
299 OpcodeForCandidate == TargetOpcode::G_SEXT)
399 ? TargetOpcode::G_SEXT
403 if (UseMI.getOpcode() == TargetOpcode::G_SEXT ||
451 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 279 case TargetOpcode::G_SEXT: {
lib/CodeGen/GlobalISel/Legalizer.cpp 73 case TargetOpcode::G_SEXT:
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 660 case TargetOpcode::G_SEXT: {
1007 MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
1570 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1571 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1582 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1638 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1743 ? TargetOpcode::G_SEXT
1754 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1782 1, TargetOpcode::G_SEXT);
1793 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1815 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
3010 case G_SEXT:
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 255 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}});
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 424 return buildInstr(TargetOpcode::G_SEXT, Res, Op);
436 return TargetOpcode::G_SEXT;
455 TargetOpcode::G_SEXT == ExtOpc) &&
477 return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
1000 case TargetOpcode::G_SEXT:
lib/CodeGen/GlobalISel/Utils.cpp 248 case TargetOpcode::G_SEXT:
280 case TargetOpcode::G_SEXT:
lib/CodeGen/MachineVerifier.cpp 1119 case TargetOpcode::G_SEXT:
lib/Target/AArch64/AArch64CallLowering.cpp 304 ExtendOp = TargetOpcode::G_SEXT;
lib/Target/AArch64/AArch64InstructionSelector.cpp 2058 case TargetOpcode::G_SEXT: {
2060 const bool IsSigned = Opcode == TargetOpcode::G_SEXT;
4501 if (Opc == TargetOpcode::G_SEXT || Opc == TargetOpcode::G_SEXT_INREG) {
lib/Target/AArch64/AArch64LegalizerInfo.cpp 371 getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 1747 case TargetOpcode::G_SEXT:
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 435 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
lib/Target/ARM/ARMInstructionSelector.cpp 345 if (Opc == G_SEXT)
860 case G_SEXT:
lib/Target/ARM/ARMLegalizerInfo.cpp 84 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
lib/Target/ARM/ARMRegisterBankInfo.cpp 249 case G_SEXT:
lib/Target/Mips/MipsLegalizerInfo.cpp 113 getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
lib/Target/X86/X86LegalizerInfo.cpp 176 setAction({G_SEXT, Ty}, Legal);
237 for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {