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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc43340 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
43375 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
43425 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
43460 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
gen/lib/Target/ARM/ARMGenGlobalISel.inc 5729 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
5769 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
5798 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5838 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6042 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6083 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6294 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
6335 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
6632 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6667 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6836 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
6871 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
gen/lib/Target/Mips/MipsGenGlobalISel.inc 724 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
752 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
880 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
907 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
12413 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
12606 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
gen/lib/Target/X86/X86GenGlobalISel.inc 4101 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
4134 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
4422 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
4520 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
4835 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
4933 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
5791 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
5824 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
5962 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
6039 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
6185 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
6262 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h 40 case TargetOpcode::G_SHL:
include/llvm/CodeGen/GlobalISel/IRTranslator.h 423 return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 1285 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
lib/CodeGen/GlobalISel/CSEInfo.cpp 41 case TargetOpcode::G_SHL:
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 150 case TargetOpcode::G_SHL:
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 310 case TargetOpcode::G_SHL: {
336 case TargetOpcode::G_SHL:
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 879 case TargetOpcode::G_SHL:
1549 case TargetOpcode::G_SHL:
2269 MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2999 case G_SHL:
3060 if (MI.getOpcode() == TargetOpcode::G_SHL) {
3182 case TargetOpcode::G_SHL: {
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 990 case TargetOpcode::G_SHL:
lib/CodeGen/GlobalISel/Utils.cpp 362 case TargetOpcode::G_SHL:
lib/Target/AArch64/AArch64InstructionSelector.cpp 454 case TargetOpcode::G_SHL:
467 case TargetOpcode::G_SHL:
1011 assert(I.getOpcode() == TargetOpcode::G_SHL);
1160 case TargetOpcode::G_SHL:
1203 assert(I.getOpcode() == TargetOpcode::G_SHL && "unexpected op");
1284 case TargetOpcode::G_SHL:
1858 case TargetOpcode::G_SHL:
1859 if (Opcode == TargetOpcode::G_SHL &&
4211 if (OffsetOpc != TargetOpcode::G_SHL && OffsetOpc != TargetOpcode::G_MUL)
4226 if (OffsetOpc == TargetOpcode::G_SHL)
4443 case TargetOpcode::G_SHL:
4588 if (RootDef->getOpcode() == TargetOpcode::G_SHL) {
lib/Target/AArch64/AArch64LegalizerInfo.cpp 96 getActionDefinitionsBuilder(G_SHL)
632 case TargetOpcode::G_SHL:
664 MI.getOpcode() == TargetOpcode::G_SHL);
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 555 case TargetOpcode::G_SHL:
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 890 auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
1169 B.buildInstr(TargetOpcode::G_SHL)
lib/Target/ARM/ARMInstructionSelector.cpp 1061 case G_SHL: {
lib/Target/ARM/ARMLegalizerInfo.cpp 102 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
lib/Target/ARM/ARMRegisterBankInfo.cpp 246 case G_SHL:
lib/Target/Mips/MipsLegalizerInfo.cpp 155 getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
lib/Target/Mips/MipsRegisterBankInfo.cpp 449 case G_SHL:
lib/Target/X86/X86LegalizerInfo.cpp 160 {G_SHL, G_LSHR, G_ASHR})
272 {G_SHL, G_LSHR, G_ASHR})
lib/Target/X86/X86RegisterBankInfo.cpp 184 case TargetOpcode::G_SHL:
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp 156 ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
161 ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),