reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
134 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); 144 << " " << printReg(r, TRI)); 154 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); 164 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { 182 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 210 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 219 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) 256 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 314 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 315 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) { 326 dbgs() << header << printReg(Reg, TRI); 334 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 342 dbgs() << header << printReg(Reg, TRI); 345 LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" 381 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" 397 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { 402 << printReg(AliasReg, TRI) << ")"); 409 RC = TII->getRegClass(MI.getDesc(), i, TRI, MF); 428 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 435 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) 477 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" 493 RC = TII->getRegClass(MI.getDesc(), i, TRI, MF); 513 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); 516 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); 526 BitVector BV(TRI->getNumRegs(), false); 536 BitVector RCBV = TRI->getAllocatableSet(MF, RC); 544 LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC)); 577 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) 582 LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":"); 591 dbgs() << " " << printReg(r, TRI); 601 bool IsSub = TRI->isSubRegister(SuperReg, Reg); 616 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) 630 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); 654 LLVM_DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':'); 666 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); 668 NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx); 671 LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI)); 688 for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) { 693 << "(alias " << printReg(AliasReg, TRI) << " live)"); 706 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI); 724 if (DefMI->readsRegister(NewReg, TRI)) { 800 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { 802 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); 807 BitVector RegAliases(TRI->getNumRegs()); 858 LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI)); 927 for (MCRegAliasIterator AI(AntiDepReg, TRI, true); AI.isValid(); ++AI) 936 if (R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R)) 961 << printReg(AntiDepReg, TRI) << ":"); 969 LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->" 970 << printReg(NewReg, TRI) << "("