|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 811 MachineInstrBuilder buildBuildVector(const DstOp &Res,
References
lib/CodeGen/GlobalISel/CombinerHelper.cpp 171 Builder.buildBuildVector(NewDstReg, Ops);
lib/CodeGen/GlobalISel/IRTranslator.cpp 2137 EntryBuilder->buildBuildVector(Reg, Ops);
2147 EntryBuilder->buildBuildVector(Reg, Ops);
2164 EntryBuilder->buildBuildVector(Reg, Ops);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 211 MIRBuilder.buildBuildVector(DstReg, PartRegs);
622 MIRBuilder.buildBuildVector(DstReg, DstRegs);
748 MIRBuilder.buildBuildVector(DstReg, DstRegs);
2307 MIRBuilder.buildBuildVector(DstReg, DstRegs);
2400 MIRBuilder.buildBuildVector(DstReg, DstRegs);
2545 MIRBuilder.buildBuildVector(DstReg, DstRegs);
2612 MIRBuilder.buildBuildVector(DstReg, DstRegs);
2684 MIRBuilder.buildBuildVector(DstReg, DstRegs);
2840 auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
3505 MIRBuilder.buildBuildVector(DstReg, DstRegs);
3580 MIRBuilder.buildBuildVector(DstReg, DstRegs);
4156 MIRBuilder.buildBuildVector(DstReg, BuildVec);
lib/Target/AArch64/AArch64CallLowering.cpp 339 .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 525 B.buildBuildVector(OrigRegs[0], Regs);
541 B.buildBuildVector(OrigRegs[0], EltMerges);
545 auto BV = B.buildBuildVector(BVType, Regs);
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1752 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0);
2071 return B.buildBuildVector(LLT::vector(NumElts, S32), WideRegs).getReg(0);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 906 auto Merge = B.buildBuildVector(OpTy, ReadlanePieces);
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 896 auto BV0 = B.buildBuildVector(V2S16, {Constant0, Constant1});
897 auto BV1 = B.buildBuildVector(V2S16, {Constant0, Constant1});