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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 683 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
References
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h 54 return buildConstant(Dst, MaybeCst->getSExtValue());
65 return buildConstant(Dst, MaybeCst->getSExtValue());
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 111 auto MIBMask = Builder.buildConstant(DstTy, Mask.getZExtValue());
211 Builder.buildConstant(DstReg, 0);
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 1341 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 162 return buildConstant(DstOps[0], Cst->getSExtValue());
173 return buildConstant(Dst, MaybeCst->getSExtValue());
lib/CodeGen/GlobalISel/CombinerHelper.cpp 1018 MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), DstOff);
1122 Offset = MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset)
1220 MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset);
1237 MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset);
lib/CodeGen/GlobalISel/IRTranslator.cpp 632 auto True = MIB.buildConstant(i1Ty, 1);
1082 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
1096 auto ElementSizeMIB = MIRBuilder.buildConstant(
1109 MIRBuilder.buildConstant(getLLTForType(*OffsetIRTy, *DL), Offset);
1437 MIRBuilder.buildConstant(Reg, TypeID);
1830 auto SAMinusOne = MIRBuilder.buildConstant(IntPtrTy, StackAlign - 1);
1834 MIRBuilder.buildConstant(IntPtrTy, ~(uint64_t)(StackAlign - 1));
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 677 MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
694 Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
972 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
1037 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1190 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1299 auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1362 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1438 {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1483 {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1505 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1527 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1956 MIRBuilder.buildConstant(Zero, 0);
1963 MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
2085 MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2091 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2151 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2157 MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2268 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
3062 Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3064 Lo = MIRBuilder.buildConstant(NVT, 0);
3068 Lo = MIRBuilder.buildConstant(NVT, 0);
3080 Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3084 Hi = MIRBuilder.buildConstant(NVT, 0);
3087 Hi = MIRBuilder.buildConstant(NVT, 0);
3101 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3106 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3110 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3167 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3176 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3191 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero.
3214 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero.
3216 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3699 auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3700 auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3722 auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3731 {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3750 auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3751 auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3763 auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3772 auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3809 auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3810 auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3814 auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3820 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3825 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3828 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3829 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3832 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3835 auto One = MIRBuilder.buildConstant(S32, 1);
3887 auto SignBit = MIRBuilder.buildConstant(S64, 63);
3896 MIRBuilder.buildConstant(S64, 0));
4002 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4008 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4090 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4150 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4217 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4249 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4286 auto Zero = MIRBuilder.buildConstant(Ty, 0);
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 244 auto Cst = buildConstant(ValueTy, Value);
lib/Target/AArch64/AArch64CallLowering.cpp 160 MIRBuilder.buildConstant(OffsetReg, Offset);
lib/Target/AArch64/AArch64LegalizerInfo.cpp 744 auto AlignMinus1 = MIRBuilder.buildConstant(IntPtrTy, Align - 1);
759 auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrSize));
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 357 B.buildConstant(OffsetReg, Offset);
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1168 auto ShiftAmt = B.buildConstant(S32, WidthM1 + 1);
1253 auto HighAddr = B.buildConstant(
1265 auto SegmentNull = B.buildConstant(DstTy, NullVal);
1266 auto FlatNull = B.buildConstant(SrcTy, 0);
1288 B.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
1290 B.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
1378 auto Const0 = B.buildConstant(S32, FractBits - 32);
1379 auto Const1 = B.buildConstant(S32, ExpBits);
1385 return B.buildSub(S32, ExpPart, B.buildConstant(S32, 1023));
1411 const auto SignBitMask = B.buildConstant(S32, UINT32_C(1) << 31);
1414 const auto FractMask = B.buildConstant(S64, (UINT64_C(1) << FractBits) - 1);
1416 const auto Zero32 = B.buildConstant(S32, 0);
1424 auto FiftyOne = B.buildConstant(S32, FractBits - 1);
1455 auto ThirtyTwo = B.buildConstant(S32, 32);
1656 B.buildConstant(DstReg, MFI->allocateLDSGlobal(B.getDataLayout(), *GV));
1808 auto ShiftAmt = B.buildConstant(S32, Shift);
1812 B.buildAnd(DstReg, AndMaskSrc, B.buildConstant(S32, Mask >> Shift));
1984 auto C0 = B.buildConstant(S32, 0x6f800000);
1985 auto C1 = B.buildConstant(S32, 0x2f800000);
1986 auto C2 = B.buildConstant(S32, FloatToBits(1.0f));
2034 B.buildGEP(DstReg, KernargPtrReg, B.buildConstant(IdxTy, Offset).getReg(0));
2195 B.buildConstant(MI.getOperand(0), ST.getWavefrontSize());
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 1101 B.buildConstant(IdxReg, DefIdx);
1217 BaseReg = B.buildConstant(S32, Overflow).getReg(0);
1219 auto OverflowVal = B.buildConstant(S32, Overflow);
1226 BaseReg = B.buildConstant(S32, 0).getReg(0);
1521 auto ShiftAmt = B.buildConstant(S32, 31);
1526 B.buildConstant(DefRegs[1], 0);
1550 auto True = B.buildConstant(SelType, Signed ? -1 : 1);
1551 auto False = B.buildConstant(SelType, 0);
1576 auto ShiftAmt = B.buildConstant(LLT::scalar(32), DstTy.getSizeInBits() - 1);
1625 auto ShiftAmt = B.buildConstant(S32, 16);
1631 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0);
1634 auto ShiftAmt = B.buildConstant(S32, 16);
1676 auto One = B.buildConstant(S32, 1);
1743 auto One = B.buildConstant(S32, 1);
lib/Target/ARM/ARMCallLowering.cpp 106 MIRBuilder.buildConstant(OffsetReg, Offset);
lib/Target/ARM/ARMLegalizerInfo.cpp 411 MIRBuilder.buildConstant(OriginalResult,
449 MIRBuilder.buildConstant(Zero, 0);
lib/Target/Mips/MipsCallLowering.cpp 299 MIRBuilder.buildConstant(OffsetReg, Offset);
lib/Target/Mips/MipsLegalizerInfo.cpp 275 {Src, MIRBuilder.buildConstant(s32, UINT32_C(0x43300000))});
lib/Target/X86/X86CallLowering.cpp 115 MIRBuilder.buildConstant(OffsetReg, Offset);
unittests/CodeGen/GlobalISel/CSETest.cpp 46 auto MIBCst = CSEB.buildConstant(s32, 0);
47 auto MIBCst1 = CSEB.buildConstant(s32, 0);
61 auto Splat0 = CSEB.buildConstant(LLT::vector(2, s32), 0);
85 auto MIBZero = B.buildConstant(s16, 0);
98 auto MIBZeroTmp = CSEB.buildConstant(s16, 0);
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp 29 CFB.buildAdd(s32, CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1));
29 CFB.buildAdd(s32, CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1));
36 {CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1)});
36 {CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1)});
48 {CFB1.buildConstant(s32, 1), CFB1.buildConstant(s32, 1)});
48 {CFB1.buildConstant(s32, 1), CFB1.buildConstant(s32, 1)});
56 {CFB1.buildConstant(s32, 0x01), uint64_t(8)});
64 {CFB1.buildConstant(s32, 0x80), uint64_t(8)});
77 auto MIBCst1 = B.buildConstant(s32, 16);
78 auto MIBCst2 = B.buildConstant(s32, 9);
unittests/CodeGen/GlobalISel/KnownBitsTest.cpp 128 auto SignBit = B.buildConstant(S32, 0x80000000);
129 auto Zero = B.buildConstant(S32, 0);
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 688 auto InitOtherVal = B.buildConstant(s64, 999);
697 auto MidOtherVal = B.buildConstant(s64, 345);
894 Register Constant0 = B.buildConstant(S16, 1).getReg(0);
895 Register Constant1 = B.buildConstant(S16, 2).getReg(0);
949 Merge0Ops.push_back(B.buildConstant(S3, I).getReg(0));
958 Merge1Ops.push_back(B.buildConstant(S3, I).getReg(0));
964 Merge2Ops.push_back(B.buildConstant(S8, I).getReg(0));
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp 17 B.buildConstant(LLT::scalar(32), 42);
20 B.buildConstant(LLT::vector(2, 32), 99);
333 Register RegC0 = B.buildConstant(S32, 0)->getOperand(0).getReg();
334 Register RegC1 = B.buildConstant(S32, 1)->getOperand(0).getReg();
335 Register RegC2 = B.buildConstant(S32, 2)->getOperand(0).getReg();
336 Register RegC3 = B.buildConstant(S32, 3)->getOperand(0).getReg();
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 37 auto MIBCst = B.buildConstant(LLT::scalar(64), 42);
80 auto MIBMul2 = B.buildMul(s64, Copies[0], B.buildConstant(s64, 42));
91 auto MIBSub = B.buildSub(s64, Copies[0], B.buildConstant(s64, 42));
97 {Copies[0], B.buildConstant(s64, 42)});
107 {Copies[0], B.buildConstant(s64, 42)});