reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

  708   MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);

References

lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp

  132       return buildCopy(Op.getReg(), MIB->getOperand(0).getReg());

lib/CodeGen/GlobalISel/CallLowering.cpp

  338           MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0));

lib/CodeGen/GlobalISel/CombinerHelper.cpp

   49     Builder.buildCopy(ToReg, FromReg);

lib/CodeGen/GlobalISel/IRTranslator.cpp

  348     MIRBuilder.buildCopy(
  351     MIRBuilder.buildCopy(
  880     MIRBuilder.buildCopy(Regs[0], VReg);
  923     MIRBuilder.buildCopy(VReg, Vals[0]);
 1031       MIRBuilder.buildCopy(Regs[0], SrcReg);
 1114   MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
 1477     MIRBuilder.buildCopy(Reg, StackPtr);
 1491     MIRBuilder.buildCopy(StackPtr, Reg);
 1557       MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt(
 1770   MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
 1778   MIRBuilder.buildCopy(PtrVReg, SelectorReg);
 1867       MIRBuilder.buildCopy(Regs[0], Elt);
 1891       MIRBuilder.buildCopy(Regs[0], Elt);

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

  714     MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
 4127     MIRBuilder.buildCopy(DstReg, Val);
 4174   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
 4189   MIRBuilder.buildCopy(SPReg, SPTmp);
 4190   MIRBuilder.buildCopy(Dst, SPTmp);

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

  495     return buildCopy(Dst, Src);

lib/Target/AArch64/AArch64CallLowering.cpp

   76       MIRBuilder.buildCopy(ValVReg, PhysReg);
   81       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
  157     MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
  173     MIRBuilder.buildCopy(PhysReg, ExtReg);
  366     MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
  412     MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
  888       MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
 1014     MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));

lib/Target/AArch64/AArch64InstructionSelector.cpp

  598   auto Copy = MIB.buildCopy({From}, {SrcReg});
 1556       MIB.buildCopy({DefReg}, {DefGPRReg});
 2393   MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0));
 2675     MIB.buildCopy(DstReg, Cmp.getReg(0));
 3985       MIRBuilder.buildCopy({SrcReg}, {I.getOperand(2)});
 4003       MIRBuilder.buildCopy({I.getOperand(0)}, {DstReg});
 4560   auto Copy = MIB.buildCopy({NarrowReg}, {ExtReg});

lib/Target/AMDGPU/AMDGPUCallLowering.cpp

   62     MIRBuilder.buildCopy(PhysReg, ExtReg);
  101       auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
  110       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
  115       MIRBuilder.buildCopy(ValVReg, PhysReg);
  331     B.buildCopy(ReturnAddrVReg, LiveInReturn);
  417     B.buildCopy(VReg, InputPtrReg);
  581     B.buildCopy(LiveInReturn, ReturnAddrReg);

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 1814     B.buildCopy(DstReg, LiveIn);
 1826     B.buildCopy(LiveIn, Arg->getRegister());

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

 1559         B.buildCopy(DefRegs[1], DefRegs[0]);

lib/Target/ARM/ARMCallLowering.cpp

  103     MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
  124     MIRBuilder.buildCopy(PhysReg, ExtReg);
  350       MIRBuilder.buildCopy(ValVReg, PhysReg);
  359       MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);

lib/Target/Mips/MipsCallLowering.cpp

  168       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
  173       MIRBuilder.buildCopy(ValVReg, PhysReg);
  282     MIRBuilder.buildCopy(PhysReg, ExtReg);
  295   MIRBuilder.buildCopy(SPReg, Register(Mips::SP));
  522           MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
  632     MIRBuilder.buildCopy(

lib/Target/X86/X86CallLowering.cpp

  112     MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
  146     MIRBuilder.buildCopy(PhysReg, ExtReg);
  274         auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
  279       MIRBuilder.buildCopy(ValVReg, PhysReg);
  285       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);