reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
333 MachineInstrBuilder buildInstr(unsigned Opcode);
716 auto MIB = MIRBuilder.buildInstr(NewOpcode);
lib/CodeGen/GlobalISel/IRTranslator.cpp1169 auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD); 1189 MIRBuilder.buildInstr(Op) 1313 MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI)); 1365 MIRBuilder.buildInstr(TargetOpcode::G_VASTART) 1503 MIRBuilder.buildInstr(Opcode) 1537 MIRBuilder.buildInstr(TargetOpcode::INLINEASM) 1701 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol); 1707 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol); 1751 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL) 1849 MIRBuilder.buildInstr(TargetOpcode::G_VAARG) 1919 MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)lib/CodeGen/GlobalISel/LegalizerHelper.cpp
824 MIRBuilder.buildInstr(ExtLoad) 929 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1506 MIRBuilder.buildInstr(TargetOpcode::G_LSHR) 1919 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV) 1950 MIRBuilder.buildInstr(Opcode) 1964 MIRBuilder.buildInstr(TargetOpcode::G_ASHR) 2019 MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS); 2534 MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode()) 2715 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 2786 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3330 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
131 return buildInstr(TargetOpcode::DBG_VALUE) 146 auto MIB = buildInstr(TargetOpcode::DBG_VALUE); 166 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); 175 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC); 185 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX); 198 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE); 254 auto MIB = buildInstr(TargetOpcode::G_PTR_MASK); 262 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); 267 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); 275 return buildInstr(TargetOpcode::G_BRJT) 294 auto Const = buildInstr(TargetOpcode::G_CONSTANT) 300 auto Const = buildInstr(TargetOpcode::G_CONSTANT); 326 auto Const = buildInstr(TargetOpcode::G_FCONSTANT) 333 auto Const = buildInstr(TargetOpcode::G_FCONSTANT); 365 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); 381 auto MIB = buildInstr(Opcode); 394 auto MIB = buildInstr(TargetOpcode::G_STORE); 528 auto Extract = buildInstr(TargetOpcode::G_EXTRACT); 664 return buildInstr(TargetOpcode::G_INSERT) 675 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS 687 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS 761 return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS) 787 return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG) 811 auto MIB = buildInstr(Opcode); 904 return buildInstr(TargetOpcode::G_FENCE) 915 return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); 1173 auto MIB = buildInstr(Opc);lib/Target/AArch64/AArch64CallLowering.cpp
806 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); 902 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0); 964 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); 1024 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)lib/Target/AArch64/AArch64InstructionSelector.cpp
1134 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); 3257 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addDef(ZReg).addUse(LHS.getReg());lib/Target/AMDGPU/AMDGPUCallLowering.cpp
307 B.buildInstr(AMDGPU::S_ENDPGM)
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp955 B.buildInstr(AMDGPU::V_MOV_B32_e32) 960 B.buildInstr(AMDGPU::V_MOV_B32_e32) 1011 MachineInstrBuilder MIB = B.buildInstr(Opc)lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
1163 B.buildInstr(AMDGPU::S_GETREG_B32) 1169 B.buildInstr(TargetOpcode::G_SHL) 1303 B.buildInstr(TargetOpcode::G_PTRTOINT) 1618 MachineInstrBuilder MIB = B.buildInstr(AMDGPU::SI_PC_ADD_REL_OFFSET) 1754 B.buildInstr(AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG) 2120 B.buildInstr(AMDGPU::SI_IF) 2141 B.buildInstr(AMDGPU::SI_LOOP)lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
618 B.buildInstr(AMDGPU::G_UNMERGE_VALUES) 703 B.buildInstr(TargetOpcode::IMPLICIT_DEF) 732 B.buildInstr(TargetOpcode::PHI) 740 B.buildInstr(TargetOpcode::G_PHI) 792 B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64) 802 B.buildInstr(WaveAndOpc) 886 B.buildInstr(CmpOp) 895 B.buildInstr(WaveAndOpc) 922 B.buildInstr(AndSaveExecOpc) 929 B.buildInstr(XorTermOpc) 938 B.buildInstr(AMDGPU::S_CBRANCH_EXECNZ) 947 B.buildInstr(MovTermOpc) 1008 B.buildInstr(AMDGPU::V_READFIRSTLANE_B32) 1303 MachineInstrBuilder MIB = B.buildInstr(Opc) 1420 B.buildInstr(Opc) 1425 B.buildInstr(Opc)lib/Target/ARM/ARMCallLowering.cpp
517 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN); 581 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)lib/Target/Mips/MipsCallLowering.cpp
147 .buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64 157 MIRBuilder.buildInstr(Mips::MTC1) 259 .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64 267 .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64 275 MIRBuilder.buildInstr(Mips::MFC1) 564 MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN); 666 MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);lib/Target/Mips/MipsLegalizerInfo.cpp
303 if (!MIRBuilder.buildInstr(Opcode) 318 MIRBuilder.buildInstr(Opcode) 330 MIRBuilder.buildInstr(Opcode) 357 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);lib/Target/X86/X86CallLowering.cpp
394 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); 438 MIRBuilder.buildInstr(X86::MOV8ri) 486 MIRBuilder.buildInstr(AdjStackUp)unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
701 auto Phi = B.buildInstr(TargetOpcode::G_PHI) 710 B.buildInstr(TargetOpcode::G_PHI)