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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Overridden By
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h 28 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 137 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
Declarations
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 1472 virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
References
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h 69 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps);
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 72 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc});
151 Builder.buildInstr(
204 Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {});
308 Builder.buildInstr(ConvertOp, {DstRegs[j]}, {TmpRegs[j]});
343 Builder.buildInstr(ConvertOp, {MI.getOperand(Idx).getReg()},
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 523 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
529 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
534 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
539 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
544 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
1228 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1245 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1261 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1267 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1273 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1279 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1285 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1291 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1297 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1313 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1328 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1334 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1342 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1347 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1352 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1357 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1362 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1367 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1374 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1380 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});
1386 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2});
1393 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1399 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1405 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1411 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1417 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1422 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1427 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1432 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1437 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1443 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1449 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1455 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1461 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 179 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
183 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
200 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
lib/CodeGen/GlobalISel/IRTranslator.cpp 302 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
318 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op1}, Flags);
332 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op0}, Flags);
355 MIRBuilder.buildInstr(TargetOpcode::G_FCMP, {Res}, {Pred, Op0, Op1},
633 Cond = MIB.buildInstr(TargetOpcode::G_XOR, {i1Ty}, {Cond, True}, None)
1014 MIRBuilder.buildInstr(TargetOpcode::G_SELECT, {ResRegs[i]},
1045 MIRBuilder.buildInstr(Opcode, {Res}, {Op});
1273 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
1418 MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2},
1422 auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1},
1424 MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2},
1932 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 768 MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
776 MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
1007 MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
1055 .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
1063 .buildInstr(
1084 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1091 auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1101 MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1110 MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1425 auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1427 auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1433 auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1436 auto AndOp = MIRBuilder.buildInstr(
1475 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1481 MIBNewOp = MIRBuilder.buildInstr(
2004 MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
2020 MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
2269 MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2270 MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2348 MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2365 MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2386 MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2388 MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2390 MIRBuilder.buildInstr(Opc, {DstReg},
3205 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3219 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3609 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3615 auto Inst = MIRBuilder.buildInstr(
3697 auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3723 auto MIBOp = MIRBuilder.buildInstr(
3725 {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3729 auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3730 MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3748 auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3765 MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3766 auto MIBTmp = MIRBuilder.buildInstr(
3768 {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3773 MIRBuilder.buildInstr(
3776 MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
4051 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 206 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
229 return buildInstr(TargetOpcode::G_GEP, {Res}, {Op0, Op1});
283 return buildInstr(TargetOpcode::COPY, Res, Op);
405 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
413 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
419 return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
424 return buildInstr(TargetOpcode::G_SEXT, Res, Op);
429 return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
448 return buildInstr(ExtOp, Res, Op);
472 return buildInstr(Opcode, Res, Op);
507 return buildInstr(Opcode, Dst, Src);
577 return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
587 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
597 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
616 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
625 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
631 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
641 return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
650 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
697 return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
703 return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
710 return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
719 return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
728 return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
734 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
740 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
1077 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1078 return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1140 return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
lib/Target/AArch64/AArch64CallLowering.cpp 329 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
348 MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}).getReg(0);
lib/Target/AArch64/AArch64InstructionSelector.cpp 599 auto SubRegCopy = MIB.buildInstr(TargetOpcode::COPY, {To}, {})
978 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB);
1033 auto UShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Src2Reg});
1075 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg});
1077 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg});
1122 auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {});
1183 auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {})
1221 MIB.buildInstr(Is64Bit ? AArch64::UBFMXri : AArch64::UBFMWri,
1630 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
1810 MIB.buildInstr(AArch64::SUBREG_TO_REG, {DstReg}, {})
1912 auto AddsMI = MIRBuilder.buildInstr(
1922 .buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()},
2104 MIB.buildInstr(AArch64::SUBREG_TO_REG, {&AArch64::GPR64RegClass}, {})
2109 ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMXri : AArch64::UBFMXri,
2114 ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMWri : AArch64::UBFMWri,
2342 MIB.buildInstr(AArch64::JumpTableDest32, {TargetReg, ScratchReg},
2347 MIB.buildInstr(AArch64::BR, {}, {TargetReg});
2362 MIB.buildInstr(AArch64::MOVaddrJT, {DstReg}, {})
2379 MIB.buildInstr(AArch64::LOADgot, {AArch64::X0}, {})
2382 auto Load = MIB.buildInstr(AArch64::LDRXui, {&AArch64::GPR64commonRegClass},
2389 MIB.buildInstr(AArch64::BLR, {}, {Load})
2667 auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg});
2672 Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp});
2685 auto Undef = MIRBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstRC}, {});
2690 .buildInstr(TargetOpcode::INSERT_SUBREG, {DstRC}, {Undef, Scalar})
2728 auto Tmp = MIB.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstTy}, {});
2838 auto Copy = MIRBuilder.buildInstr(TargetOpcode::COPY, {*DstReg}, {})
2856 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx);
3018 auto FirstCopy = MIB.buildInstr(TargetOpcode::COPY, {CopyTo}, {})
3081 MIRBuilder.buildInstr(AArch64::ADRP, {&AArch64::GPR64RegClass}, {})
3089 .buildInstr(AArch64::LDRQui, {&AArch64::FPR128RegClass}, {Adrp})
3095 .buildInstr(AArch64::LDRDui, {&AArch64::FPR64RegClass}, {Adrp})
3155 auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS.getReg()});
3181 auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS.getReg()});
3211 auto TstMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS});
3323 .buildInstr(InsertOpc, {*Dst}, {WidenedOp1->getOperand(0).getReg()})
3372 .buildInstr(AArch64::CSINCWr, {DefReg}, {Register(AArch64::WZR), Register(AArch64::WZR)})
3458 auto Cmp = MIB.buildInstr(CmpOpc, {}, {CondDef->getOperand(2).getReg()});
3467 MIB.buildInstr(CSelOpc, {I.getOperand(0).getReg()},
3631 auto Dup = MIB.buildInstr(Opc, {I.getOperand(0).getReg()}, {ScalarReg});
3710 auto TBL1 = MIRBuilder.buildInstr(
3717 .buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
3727 .buildInstr(TargetOpcode::REG_SEQUENCE,
3734 MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0).getReg()},
3759 InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg})
3764 InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg})
3836 MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})
3908 MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})
3949 MIRBuilder.buildInstr(AArch64::BRK, {}, {}).addImm(1);
3954 MIRBuilder.buildInstr(AArch64::BRK, {}, {}).addImm(0xF000);
3996 auto SHA1Inst = MIRBuilder.buildInstr(AArch64::SHA1Hrr, {DstReg}, {SrcReg});
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1358 auto Trunc = B.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {S64}, {Src});
lib/Target/Mips/MipsInstructionSelector.cpp 134 MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
140 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {})
146 MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
152 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {})
154 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg})
489 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg});
502 MachineInstrBuilder PairF64 = B.buildInstr(
691 MachineInstrBuilder MIB = B.buildInstr(
lib/Target/Mips/MipsLegalizerInfo.cpp 273 MachineInstrBuilder Bitcast = MIRBuilder.buildInstr(
unittests/CodeGen/GlobalISel/CSETest.cpp 21 auto MIBInput = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[0]});
22 auto MIBInput1 = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[1]});
23 auto MIBAdd = B.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput});
83 auto MIBInput = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[0]});
84 auto MIBAdd = B.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput});
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 39 B.buildInstr(TargetOpcode::G_CTTZ, {LLT::scalar(64)}, {Copies[0]});
71 B.buildInstr(TargetOpcode::G_CTTZ, {LLT::scalar(64)}, {Copies[0]});
105 B.buildInstr(TargetOpcode::G_CTTZ, {LLT::scalar(64)}, {Copies[0]});
139 auto MIBCTPOP = B.buildInstr(TargetOpcode::G_CTPOP, {s16}, {MIBTrunc});
172 auto MIBCTPOP = B.buildInstr(TargetOpcode::G_CTPOP, {s32}, {MIBTrunc});
200 auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
228 B.buildInstr(TargetOpcode::G_CTLZ, {LLT::scalar(64)}, {Copies[0]});
259 B.buildInstr(TargetOpcode::G_CTLZ, {LLT::scalar(64)}, {Copies[0]});
292 auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, {s8}, {MIBTrunc});
334 auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, {s8}, {MIBTrunc});
370 B.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {s8}, {MIBTrunc});
405 auto MIBCTPOP = B.buildInstr(TargetOpcode::G_CTPOP, {s8}, {MIBTrunc});
439 B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {s8}, {MIBTrunc});
472 auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ, {s8}, {MIBTrunc});
508 B.buildInstr(TargetOpcode::G_UADDO, {s8, CarryReg}, {MIBTrunc, MIBTrunc});
547 B.buildInstr(TargetOpcode::G_USUBO, {s8, CarryReg}, {MIBTrunc, MIBTrunc});
763 B.buildInstr(TargetOpcode::G_FADD, {LLT::scalar(64)}, {Copies[0], Copies[1]},
768 B.buildInstr(TargetOpcode::G_FNEG, {LLT::scalar(64)}, {FAdd.getReg(0)},
773 B.buildInstr(TargetOpcode::G_FNEG, {LLT::scalar(64)}, {Copies[0]},
1068 auto MIB = B.buildInstr(
1070 {B.buildInstr(TargetOpcode::G_TRUNC, {LLT::scalar(32)}, {Copies[0]}),
1099 auto MIB = B.buildInstr(
1101 {B.buildInstr(TargetOpcode::G_TRUNC, {LLT::scalar(16)}, {Copies[0]}),
1129 auto MIB = B.buildInstr(
1131 {B.buildInstr(TargetOpcode::G_TRUNC, {LLT::scalar(32)}, {Copies[0]}),
1161 auto MIB = B.buildInstr(
1163 {B.buildInstr(TargetOpcode::G_TRUNC, {LLT::scalar(32)}, {Copies[0]}),
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 96 auto MIBFMul = B.buildInstr(TargetOpcode::G_FMUL, {s64},
106 auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, {s64},
142 auto MIBFabs = B.buildInstr(TargetOpcode::G_FABS, {s32}, {Copy0s32});
148 auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32});