reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
301 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) 305 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) 412 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot, 418 HSpiller.addToMergeableSpills(*MII, StackSlot, Original); 471 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) { 477 if (HSpiller.rmFromMergeableSpills(MI, StackSlot)) 726 if (InstrReg != Reg || FI != StackSlot) 730 HSpiller.rmFromMergeableSpills(*MI, StackSlot); 839 : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS, &VRM); 897 HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original); 909 TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot, 949 TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot, 958 HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original); 977 buildDbgValueForSpill(*MBB, MI, *MI, StackSlot); 1065 if (StackSlot == VirtRegMap::NO_STACK_SLOT) { 1066 StackSlot = VRM.assignVirt2StackSlot(Original); 1067 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); 1070 StackInt = &LSS.getInterval(StackSlot); 1073 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot); 1116 StackSlot = VRM.getStackSlot(Original);