reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1594 const MachineInstr *MI = MO->getParent(); 1598 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0; 1603 if (!MO->isReg()) 1604 report("Explicit definition must be a register", MO, MONum); 1605 else if (!MO->isDef() && !MCOI.isOptionalDef()) 1606 report("Explicit definition marked as use", MO, MONum); 1607 else if (MO->isImplicit()) 1608 report("Explicit definition marked as implicit", MO, MONum); 1613 if (MO->isReg() && 1615 if (MO->isDef() && !MCOI.isOptionalDef()) 1616 report("Explicit operand marked as def", MO, MONum); 1617 if (MO->isImplicit()) 1618 report("Explicit operand marked as implicit", MO, MONum); 1623 if (!MO->isReg()) 1624 report("Tied use must be a register", MO, MONum); 1625 else if (!MO->isTied()) 1626 report("Operand should be tied", MO, MONum); 1628 report("Tied def doesn't match MCInstrDesc", MO, MONum); 1629 else if (Register::isPhysicalRegister(MO->getReg())) { 1634 MO->getReg() != MOTied.getReg()) 1637 } else if (MO->isReg() && MO->isTied()) 1637 } else if (MO->isReg() && MO->isTied()) 1638 report("Explicit operand should not be tied", MO, MONum); 1641 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg()) 1641 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg()) 1641 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg()) 1642 report("Extra explicit operand on non-variadic instruction", MO, MONum); 1645 switch (MO->getType()) { 1647 const Register Reg = MO->getReg(); 1651 checkLiveness(MO, MONum); 1654 if (MO->isTied()) { 1658 report("Must be tied to a register", MO, MONum); 1660 report("Missing tie flags on tied operand", MO, MONum); 1662 report("Inconsistent tie links", MO, MONum); 1667 MO, MONum); 1670 report("Explicit def should be tied to implicit use", MO, MONum); 1677 if (!MRI->isSSA() && MO->isUse() && 1680 report("Two-address instruction operands must be identical", MO, MONum); 1683 unsigned SubIdx = MO->getSubReg(); 1687 report("Illegal subregister index for physical register", MO, MONum); 1694 report("Illegal physical register for instruction", MO, MONum); 1700 if (MO->isRenamable()) { 1702 report("isRenamable set on reserved register", MO, MONum); 1706 if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) { 1706 if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) { 1707 report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum); 1719 MO, MONum); 1726 report("Generic virtual register must have a valid type", MO, 1737 MO, MONum); 1744 report("Register bank is too small for virtual register", MO, 1752 report("Generic virtual register does not allow subregister index", MO, 1763 report("Virtual register does not match instruction constraint", MO, 1778 report("Invalid subregister index for virtual register", MO, MONum); 1784 report("Invalid register class for subregister index", MO, MONum); 1797 report("No largest legal super class exists.", MO, MONum); 1802 report("No matching super-reg register class.", MO, MONum); 1807 report("Illegal virtual register for instruction", MO, MONum); 1819 regMasks.push_back(MO->getRegMask()); 1823 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent())) 1824 report("PHI operand is not in the CFG", MO, MONum); 1828 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && 1830 int FI = MO->getIndex(); 1858 report("Instruction loads from dead spill slot", MO, MONum); 1862 report("Instruction stores to dead spill slot", MO, MONum);