reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
10954 if (N0.isUndef()) 10965 (!LegalOperations && VT.isInteger() && N0.getValueType().isInteger() && 10967 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 10967 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 10968 cast<BuildVectorSDNode>(N0)->isConstant()) 10969 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), 10973 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 10973 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 10978 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() && 10980 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() && 10982 SDValue C = DAG.getBitcast(VT, N0); 10989 if (N0.getOpcode() == ISD::BITCAST) 10990 return DAG.getBitcast(VT, N0.getOperand(0)); 10994 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 10994 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 10996 TLI.hasBigEndianPartOrdering(N0.getValueType(), DAG.getDataLayout()) == 11003 ((!LegalOperations && cast<LoadSDNode>(N0)->isSimple()) || 11005 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 11007 if (TLI.isLoadBitCastBeneficial(N0.getValueType(), VT, DAG, 11013 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 11033 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || 11033 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || 11034 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && 11034 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && 11035 N0.getNode()->hasOneUse() && VT.isInteger() && 11036 !VT.isVector() && !N0.getValueType().isVector()) { 11037 SDValue NewConv = DAG.getBitcast(VT, N0.getOperand(0)); 11041 if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) { 11044 APInt::getSignMask(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64); 11046 if (N0.getOpcode() == ISD::FNEG) { 11050 assert(N0.getOpcode() == ISD::FABS); 11056 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit); 11060 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); 11065 if (N0.getOpcode() == ISD::FNEG) 11068 assert(N0.getOpcode() == ISD::FABS); 11084 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 11084 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 11085 isa<ConstantFPSDNode>(N0.getOperand(0)) && 11087 unsigned OrigXWidth = N0.getOperand(1).getValueSizeInBits(); 11090 SDValue X = DAG.getBitcast(IntXVT, N0.getOperand(1)); 11111 if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) { 11113 SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); 11115 SDValue X = DAG.getBitcast(VT, N0.getOperand(1)); 11117 SDValue XorResult = DAG.getNode(ISD::XOR, SDLoc(N0), VT, Cst, X); 11129 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); 11138 SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); 11148 if (N0.getOpcode() == ISD::BUILD_PAIR) 11149 if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT)) 11157 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && 11157 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && 11158 VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() && 11159 !(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) { 11160 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N0); 11177 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0)); 11178 SDValue SV1 = PeekThroughBitcast(N0->getOperand(1)); 11183 VT.getVectorNumElements() / N0.getValueType().getVectorNumElements();